Full Scan Design Research Articles

Single Cycle Access Structure for Logic Test

This paper proposes a new single cycle access test structure for logic test. It eliminates the peak power consumption problem of conventional shift-based scan chains and reduces the activity during shift and capture cycles. This leads to more realistic circuit behavior during stuck-at and at-speed tests. It enables the complete test to run at much higher frequencies equal or close to the one in functional mode. It will be shown, that a lesser number of test cycles can be achieved compared to other published solutions. The test cycles per net based on a simple test pattern generator algorithm without test pattern compression is below 1 for larger designs and is independent of the design size. Results are compared to other published solutions on ISCAS'89 netlists. The structure allows an additional on-chip debugging signal visibility for each register. The method is backward compatible to full scan designs and existing test pattern generators and simulators can be used with a minor enhancement. It is shown how to combine the proposed solution with built-in self test (BIST) and massive parallel scan chains.

An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology

This paper presents a scan chain design for dual-rail asynchronous circuits. This is a true asynchronous scan chain because no clock is needed even in scan mode. This is a full-scan design for testability (DfT) so only combinational automatic test pattern generation (ATPG) is needed and the fault coverage of generated test patterns is very high. This technique can be applied to various kinds of asynchronous circuits, including pipelines, state machines, and interconnects. Experiments on an 8051 datapath circuit show that the coverage is as high as 99.59%. This technique has been proven to work successfully in 8 μm Thin-film transistor (TFT) technology on the glass.

F-Scan: A DFT Method for Functional Scan at RTL

Due to the difficulty of test pattern generation for sequential circuits, several design-for-testability (DFT) approaches have been proposed. An improvement to these current approaches is needed to cater to the requirements of today's more complicated chips. This paper introduces a new DFT method applicable to high-level description of circuits, which optimally utilizes existing functional elements and paths for test. This technique, called F-scan, effectively reduces the hardware overhead due to test without compromising fault coverage. Test application time is also kept at the minimum. The comparison of F-scan with the performance of gate-level full scan design is shown through the experimental results.

VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG

IC testing based on a full-scan design methodology and ATPG is the most widely used test strategy today. However, rapidly growing test costs are severely challenging the applicability of scan-based testing. Both test data size and number of test cycles increase drastically as circuit size grows and feature size shrinks. For a full-scan circuit, test data volume and test cycle count are both proportional to the number of test patterns N and the longest scan chain length L. To reduce test data volume and test cycle count, we can reduce N, L, or both. Earlier proposals focused on reducing the number of test patterns N through pattern compaction. All these proposals assume a 1-to-1 scan configuration, in which the number of internal scan chains equals the number of external scan I/O ports or test channels (two ports per channel) from ATE. Some have shown that ATPG for a circuit with multiple clocks using the multicapture clocking scheme, as opposed to one-hot clocking, generates a reduced number of test patterns.

Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction

A new scan architecture called reconfigured scan forest is proposed for cost-effective scan testing. Multiple scan flip-flops can be grouped based on structural analysis that avoids new untestable faults due to new reconvergent fanouts. The proposed new scan architecture allows only a few scan flip-flops to be connected to the XOR trees. The size of the XOR trees can be greatly reduced compared with the original scan forest; therefore, area overhead and routing complexity can be greatly reduced. It is shown that test application cost, test data volume, and test power with the proposed scan forest architecture can be greatly reduced compared with the conventional full scan design with a single scan chain and several recent scan testing methods

Scan-BIST based on cluster analysis and the encoding of repeating sequences

We present a built-in self-test (BIST) approach for full-scan designs that extracts the most frequently occurring sequences from deterministic test patterns. The extracted sequences are stored on-chip, and are used during test application. Three sets of test patterns are applied to the circuit under test during a BIST test session; these include pseudorandom patterns, semirandom patterns, and deterministic patterns. The semirandom patterns are generated based on the stored sequences and they are more likely to detect hard-to-detect faults than pseudorandom patterns. The deterministic patterns are encoded using either the stored sequences or the LFSR reseeding technique to reduce test data volume. We use the cluster analysis technique for sequence extraction to reduce the amount of data to be stored. Experimental results for the ISCAS-89 benchmark circuits show that the proposed approach often requires less on-chip storage and test data volume than other recent BIST methods.

Scan-BIST based on cluster analysis and the encoding of repeating sequences

We present a built-in self-test (BIST) approach for full-scan designs that extracts the most frequently occurring sequences from deterministic test patterns. The extracted sequences are stored on-chip, and are used during test application. Three sets of test patterns are applied to the circuit under test during a BIST test session; these include pseudorandom patterns, semirandom patterns, and deterministic patterns. The semirandom patterns are generated based on the stored sequences and they are more likely to detect hard-to-detect faults than pseudorandom patterns. The deterministic patterns are encoded using either the stored sequences or the LFSR reseeding technique to reduce test data volume. We use the cluster analysis technique for sequence extraction to reduce the amount of data to be stored. Experimental results for the ISCAS-89 benchmark circuits show that the proposed approach often requires less on-chip storage and test data volume than other recent BIST methods.

Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults

Fault diagnosis of full-scan designs has been progressed significantly. However, most existing techniques are aimed at a logic block with a single fault. Strategies on top of these block-level techniques are needed in order to successfully diagnose a large chip with multiple faults. In this paper, we present such a strategy. Our strategy is effective in identifying more than one fault accurately. It proceeds in two phases. In the first phase we concentrate on the identification of the so-called structurally independent faults based on a concept referred to as word-level prime candidate, while in the second phase we further trace the locations of the more elusive structural dependent faults. Experimental results show that this strategy is able to find 3 to 4 faults within 10 signal inspections for three real-life designs randomly injected with 5 node-type or stuck-at faults.

Efficient Double Fault Diagnosis for CMOS Logic Circuits with a Specific Application to Generic Bridging Faults

Fault diagnosis that predicts the most likely fault sites in a faulty chip is an important step for manufacturing yield improvement or design debugging. In this paper, we address the problem of double fault diagnosis for full-scan designs. Our algorithm aims to identify both faults accurately. The features of our algorithm include the following. (1) The proposed algorithm is not limited to any particular fault type. (2) An effective selection heuristic is incorporated to significantly reduce the diagnosis time, while retaining a high success rate of catching faults. (3) The inject-and-evaluate paradigm proposed in [6] is incorporated to accurately screen out unlikely fault candidates. Experimental results on ISCAS85 benchmark circuits injected with a generic bridging fault, two stuck-at faults, or two gate-type faults show that both faults can be caught simultaneously within several minutes with a high success rate.

Enhanced Reduced Pin-Count Test for Full-Scan Design

This paper presents enhanced reduced pin-count test (E-RPCT) for low-cost test. E-RPCT is an extension of traditional RPCT for circuits in which a large number of digital IC pins is multiplexed for scan. The basic concept of E-RPCT is to provide access to the internal scan chains via an IEEE 1149.1 compatible boundary-scan architecture, instead of direct access via the IC pins. The boundary-scan chain performs serial/parallel conversion of test data. E-RPCT also provides I/O wrap to test non-contacted pins. The paper presents E-RPCT for full-scan design, as well as for full-scan core-based design.

A partial scan design unifying structural analysis and testabilities

To overcome the large extra hardware overhead attendant in full scan design, the concept of partial scan designs has emerged with the virtue of less area and testability close to full scan. Two typical partial scan techniques, based on structural analysis and testabilities, are widely adopted. The structural analysis requires less searching time, however in general the fault coverage is lower. On the other hand, the techniques using testabilities result in higher fault coverage, but require an extraordinary amount of searching time. In this paper we have analysed and unified the strength of techniques using structural analysis and testabilities. The new partial scan design proposed not only reduces the time for selecting scan flip-flop but also preserves high fault coverage. Test results demonstrate the high fault coverage and remarkable reduction in time for most ISCAS89 benchmark circuits.

Limited maximum fault-multiplicity diagnosis procedure for scan designs

A new effect-cause approach to multiple fault diagnosis in digital circuits is presented. The previous elimination algorithm is extended to sequential circuits. A new procedure capable of diagnosing any `stuck-at' type fault with limited maximum multiplicity in full scan or partial scan designs is developed. The limit is established for each logic partition of the circuit. With this new algorithm, any trial that would lead to faults of multiplicity greater than the established limit is determined a priori and is rejected. This greatly reduces the diagnostic computing time, without affecting its utility, and without probing any internal line. It can also obtain masked faults with or without a multiplicity limit. Experimental results for some full scan circuits from the ISCAS'89 benchmarks are included.

On the use of fully specified initial states for testing of synchronous sequential circuits

Full scan design renders every combinationally irredundant fault in a synchronous sequential circuit testable. In this paper, we derive a similar result applicable to design-for-testability techniques that only controls the initial state of the circuit in order to improve its testability. Examples of such techniques are parallel load, reset, and scan when it is used only to set the state of the circuit. We show that if the initial state can be set arbitrarily, a test sequence can be generated for every irredundant fault, i.e., for every fault that is not sequentially or combinationally redundant. Thus, the ability to control the state of the circuit is sufficient for detecting every irredundant fault and observability of the circuit state is not necessary for this purpose. When considering scan, this result implies that scan-out can be used to control the test length and test generation time, but it is not necessary for detecting irredundant faults. We also show that, of all the states of the circuit, it is sufficient to consider as possible initial states (or controllable states) only the states extracted from a complete combinational test set. We demonstrate the use of these observations by presenting experimental results of two applications. In the first application, initial states are selected out of a combinational test set to facilitate deterministic test generation for irredundant faults. In the second application, the ability to set the initial state is used to increase the effectiveness of built-in self-test.

Partial scan design based on levellised combinational structure

To overcome the large hardware overhead attendant in the full scan design, the concept of partial scan design has emerged with the virtue of less area and testability close to full scan. A ‘combinational structure’ has been developed to avoid the use of a sequential test generator. But test patterns shifted on the scan register have to be held for a sequential depth period upon the aid of the dedicated HOLD circuit. In this paper a new levellised structure is introduced aiming to exclude the need for an extra HOLD circuit. The time to stimulate each scan latch is uniquely determined on this structure, hence each test pattern can be applied by scan shifting and then pulsing a system clock like the full scan, but with many fewer scan flip-flops. Experimental results show that some sequential circuits are levellised by just scanning self-loop flip-flops.

Test-point insertion: scan paths through functional logic

Conventional scan design imposes considerable area and delay overheads. To establish a scan chain in the test mode, multiplexers at the inputs of flip-flops and scan wires are added to the actual design. We propose a low-overhead scan design methodology that employs a new test-point insertion technique. Unlike the conventional test-point insertion, where test points are used directly to increase the controllability and observability of the selected signals, the test points are used here to establish scan paths through the functional logic. The proposed technique reuses the functional logic for scan operations; as a result, the design-for-testability overhead on area or timing can be minimized. We show an algorithm that uses the new test-point insertion technique to reduce the area overhead for the full-scan design. We also discuss its application to the timing-driven partial-scan design.

Cost-free scan: a low-overhead scan path design

Conventional scan design imposes considerable area and delay overheads. To establish a scan chain in the test mode, multiplexers at the inputs of flip-flops and scan wires are added to the actual design. However, the functionality of the functional logic has not been utilized for the test purposes. We propose a low-overhead scan design methodology, called cost-free scan, which exploits the controllability of primary inputs to establish scan paths through the functional logic. We show how to analyze the circuit to determine all the free-scan flip-flops and select the best input vector to establish the maximum number of free-scan flip-flops for the scan chain design. Significant reduction in the scan overhead is achieved on ISCAS89 benchmarks. In full-scan designs, as many as 89% of the flip-flops are found free-scannable. In the partial-scan designs, we assume that selecting flip-flops for scan to break sequential cycles is used to increase circuit testability. Reduction can be as high as 97% in scan flip-flops needed to break sequential cycles.

Test application time reduction for sequential circuits with scan

Scan designs alleviate the test generation problem for sequential circuits. However, scan operations substantially increase the total number of test clocks during test application stage. Classical methods used to solve this problem perform test compaction and obtain fewer test vectors. In this paper we show that such a strategy does not always reduce the test clocks or test application time. Our approach is to associate a scan strategy function with each test vector during test generation for circuits with full or partial scan. The paper presents two algorithms to generate test sequences that reduce the number of test clocks required to apply the test sequences. The algorithms are based on: (1) heuristics that determine the need for scan operations; and (2) controlling sequential test generation process by choosing an appropriate target fault. In this paper we define and investigate different scan strategies for full and partial scan designs. We propose approximate measures that can be used for selection of a target fault during sequential test generation. These concepts are integrated into the algorithms Test Application time Reduction for Full scan (TARF) and Test Application time Reduction for Partial scan (TARP). The algorithms are implemented, and their efficiencies are demonstrated by using them for a set of ISCAS sequential benchmark circuits. The experiments show that, in full scan designs, TARF generated vectors require 36% fewer test clocks compared to the vectors from COMPACTEST that produces near optimal test sets. Similarly for partial scan designs, TARP achieves over 30% cumulative test clock reduction compared to the results from FASTEST which produced generally fewer vectors than other ATPG systems.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A partition and resynthesis approach to testable design of large circuits

We present a new area-efficient procedure for embedding test function into the gate-level implementation of a sequential circuit. First, we develop a test machine embedding technique for a given gate-level implementation of a finite state machine. The test machine states are mapped onto the states of the given circuit such that a minimum number of new state variable dependencies are introduced. The composite function is optimized. Experimental results show that our method yields testable machine implementations that have lower area than the corresponding full scan designs. The test generation complexity for our machine implementation is the same as that for a full scan design. To apply the method to large gate-level designs, we partition the circuit into interconnected finite-state machines. Each component state machine can be specified either as its gate-level implementation or as the extracted state diagram. We incorporate test functions into each component finite state machine such that the entire interconnection of the augmented components has the same testability properties as the product machine with a single test function. ISCAS '89 benchmark circuits are partitioned into component finite state machines using a new testability-directed partitioning algorithm. Again, our embedding procedure results in testable circuits that have lower area than the corresponding full scan designs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Test function embedding algorithms with application to interconnected finite state machines

We present new algorithms for embedding test functions into the state diagram of a finite state machine. We first identify the cases where test functions can be embedded into the state diagram of the given object machine without using an extra input line. When such embedding is possible, our method finds it. In other cases, an extra input line must be added to the object machine to make the embedding possible. For the extra input case, we use partition theory and state variable dependencies in the object machine to obtain a mapping of the test machine states onto the object machine states. This mapping introduces a minimum number of extra state variable dependencies in the augmented machine as compared to the dependencies in the object machine. Experimental results on several MCNC benchmarks show that our method yields augmented machine implementations that have lower area than corresponding full scan designs. The test generation complexity for the augmented machine implementation is the same as that for a full scan design. We further consider the embedding of test functions into machines specified as an interconnection of finite state machines. We incorporate test functions into each component finite state machine such that the augmented interconnected machine has the same testability properties as the product machine with test function.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A power-efficient channel coder/decoder chip for GSM terminals

A compact power- and computing-delay-efficient channel codec chip for the Pan-European digital cellular radio (GSM) system is presented. This key component for the hand-portable mobile station, mainly implementing GSM Recommendation 5.03 on a full duplex basis, is accomplished through a dedicated architecture and application tailored memories. An important effort was made to increase the testability of the design; the sequentiality, the low pin count, and the presence of embedded macro functions implied the need for internal scan and BIST techniques. Full scan design and self-test facilities, supported by automatic test pattern generating software, resulted in time- and coverage-efficient testing. The chip is fabricated in a double-metal 1.2- mu m CMOS technology, using a cell-based design approach incorporating memory and programmable array macro blocks. A full-rate speech channel block is decoded in less than 1.8 ms and typical average in-system power consumption does not exceed 10 mW.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>