Full Output Voltage Research Articles

Design of Low-Noise CMOS Image Sensor Using a Hybrid-Correlated Multiple Sampling Technique

We present a 320 × 240 CMOS image sensor (CIS) using the proposed hybrid-correlated multiple sampling (HMS) technique with an adaptive dual-gain analog-to-digital converter (ADC). The proposed HMS improves the noise characteristics under low illumination by adjusting the ADC gain according to the incident light on the pixels. Depending on whether it is less than or greater than 1/4 of the full output voltage range from pixels, either correlated multiple sampling or conventional-correlated double sampling (CDS) is used with different slopes of the ramping signals. The proposed CIS achieves 11-bit resolution of the ADC using an up-down counter that controls the LSB depending on the ramping signals used. The sensor was fabricated using a 0.11 μm CIS process, and the total chip area was 2.55 mm × 4.3 mm. Compared to the conventional CDS, the measurement results showed that the maximum dark random noise was reduced by 26.7% with the proposed HMS, and the maximum figure of merit was improved by 49.1%. The total power consumption was 5.1 mW at 19 frames per second with analog, pixel, and digital supply voltages of 3.3 V, 3.3 V, and 1.5 V, respectively.

A Minimum ZVS Current Control Strategy of Semi Bridgeless Active Rectifier for Wide Operation Range Based on LCC-S Compensated WPT System

To meet the requirement of the battery charging characteristics and electric vehicle interoperability, wide power range and wide voltage range are important for the wireless electric vehicle (EV) charging system. Hence, ensuring zero voltage switching (ZVS) and high efficiency over the wide operating range is a hot issue but not well resolved. To address the current state of research, an efficiency-oriented control strategy is proposed for LCC-S compensated Wireless Power Transfer (WPT) system to achieve minimum ZVS current over a wide voltage and power regulation range. Based on the accurate harmonic-considered time-domain model, a universal design method for system parameters under the worst ZVS current conditions within wide operation range is proposed. Then, the universal explicit expression at the unit voltage gain point is given. Moreover, based on the simplified fitting method of piecewise bi-quadratic interpolation (PBQI), minimum ZVS current and minimum non-active current can be ensured over the full output voltage and output power range. A 3.3 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> W prototype has been built to verify that the converter can realize ZVS within the whole voltage range, the measured peak efficiency is about 95.2%.

Design of High Speed and Area Efficient N-Bit Digital Comparator

Abstract: A digital comparator is a hardware electronic device or a combinational logic circuit. It is capable of comparing two numbers as input in binary form and determines the output. In the previous designs like in the design of XOR-XNOR(XE) with cross-coupled p-MOS, even though it occupies less area, the full swing output voltage can’t be able to produce which creates a problem when the bit width increases. To avoid this kind of disadvantages we are designing a N-bit digital comparator in a way such that it produces full swing output voltage with the improved power efficiency as well as the transistor count in the circuit also decreases. So that it can be used in several applications like scientific computations and test circuit applications etc.

A Resonant Push–Pull DC–DC Converter With an Intrinsic Current Source Behavior for Radio Frequency Power Conversion

In this article, a resonant push–pull dc–dc converter suitable for switching frequencies in the MHz-range is investigated. Despite a simple design procedure with no need of multiresonant tuning, the converter topology is capable of providing a constant output current over a wide output voltage range in unregulated operation. Based on an analytical solution of steady-state operation, normalized dependencies of converter behavior are determined and used to formulate generalized design considerations. In order to verify the theoretical analysis, the design procedure of a 300-W prototype operating at a switching frequency of 6.78 MHz is described considering the impact of circuit parasitics on converter operation. The prototype provides a stable operation within the full output voltage range of 0–150 V and reaches a peak efficiency of 93% at the nominal output voltage. A rapid transient response of the converter is demonstrated by applying a closed-loop <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> / <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> -control to the prototype.

High Performance Bulk Driven Operational Trans Conductance Amplifier and Applications

In this paper a bulk driven Fully cascoded operational transconductance amplifier(FCOTA) is designed. OTA applications are designed for voltage controlled current amplifier, filters and analog subtractor. With the current sizing method, all transistors in FCOTA work under weak inversion field. The total current in the proposed amplifier in terms of nano amperes only. As part of low power the circuit operated with the power supply of 0.8V. The main important features of the design are good linearity and accuracy. Full input and output voltage swings. This circuit has been constructed using CMOS technology with UMC90 nm. The circuit’s total power consumption is 620nW

Low Voltage Full Swing Fin FET Hybrid Full Adder

In this research paper, CMOS and FinFET based hybrid Full Adders operating at low voltages with low power dissipation are proposed. The proposed CMOS based circuit is compared with few existing hybrid full adders in terms of average power dissipation and power-delay-product (PDP). The designed CMOS based hybrid adder achieves lower power dissipation and low PDP compared to other hybrid adders over a voltage range of 0.6V to 1V. The proposed CMOS implementation of hybrid full adder fails at 0.5V to produce full swing output. To solve this full swing problem, the proposed hybrid full adder is implemented using FinFETs which produce full output voltage, lower power and low PDP comparing with CMOS implementation. The circuits are designed with HSPICE tool in 32nm predictive technology model (PTM).

Predictive ZVS Control With Improved ZVS Time Margin and Limited Variable Frequency Range for a 99% Efficient, 130-W/in3 MHz GaN Totem-Pole PFC Rectifier

This paper proposes a predictive zero-voltage-switching (ZVS) control with improved ZVS time margin and limited variable switching frequency range for a 99% efficient megahertz (MHz) GaN totem-pole power-factor-correction (PFC) rectifier. The conventional ZVS control methods for totem-pole PFC may lead to zero ZVS time margin and ultra-wide switching frequency range. This paper proposes that the synchronous rectifier (SR) turn- off current is a new degree of freedom for the ZVS control. Thus, the proposed cycle-by-cycle predictive ZVS control method controls the SR turn- off currents to extend the ZVS time margin and to reduce the maximum switching frequency. With the proposed ZVS control, the minimum ZVS time margin and a limited maximum switching frequency can be realized in a MHz GaN-based totem-pole PFC. With the improved ZVS time margin, the reliability for realizing ZVS is significantly improved. With the limited maximum frequency and the limited frequency range, the difficulty in high-speed current sensing and digital control is reduced, and the frequency-related loss is also reduced, which is important for improving the light-load efficiency. To accurately extract the current and timing parameters for the proposed ZVS control, an analytical model for the ZVS totem-pole PFC is proposed. The proposed ZVS control and analytical model are applicable over the full input and output voltage range, and over the full load range. In addition, a hybrid current control is proposed and implemented based on the proposed ZVS control. Finally, a 3.2-kW MHz GaN totem-pole PFC prototype is developed and tested with full-range ZVS, minimum ZVS time margin, limited switching frequency range, 99% peak efficiency, and 130-W/in3 power density based on the proposed ZVS control and system control strategy. The realized efficiency, power level, and power density are among the best ever reported for the GaN-based totem-pole PFC.

An Advanced Three-Level Active Neutral-Point-Clamped Converter With Improved Fault-Tolerant Capabilities

A resilient fault-tolerant silicon carbide (SiC) three-level power converter topology is introduced based on the traditional active neutral-point-clamped converter. This novel converter topology incorporates a redundant leg to provide fault tolerance during switch open-circuit faults and short-circuit faults. Additionally, the topology is capable of maintaining full output voltage and maximum modulation index in the presence of switch open and short-circuit faults. Moreover, the redundant leg can be employed to share load current with other phase legs to balance thermal stress among semiconductor switches during normal operation. A 25-kW prototype of the novel topology was designed and constructed utilizing 1.2-kV SiC metal–oxide–semiconductor field-effect transistors. Experimental results confirm the anticipated theoretical capabilities of this new three-level converter topology.

Technical method of improving overload of pressure sensitive chip based on sacrificial layer technology

For pressure sensitive chips made by sacrificial layer technology, their overload capacity can be significantly improved through accurate control over the thickness of the sacrificial layer and the pressure sensitive diaphragm. Based on the analysis for the simulation of the stress distribution of the pressure sensitive structure, the relationship between sizes of the sensitive structure and the overload capacity is elaborated in virtue of the influence of sensitive structure sizes on fracture strength of the polysilicon sensitive diaphragm; and then a design method in improving overload capacity is proposed. Our simulation and analysis indicate that the overload can exceed thirty one-fold of the full scale pressure when properly reducing the thickness of the sacrificial layer and the diaphragm. A sample pressure sensor chip is fabricated with a full scale range of 2 MPa. The test results show that the overpressure of the sample is 18MPa, and its full scale output voltage is 288 mV under 5 V power supply.

Variable-Switching-Frequency State-Feedback Control of a Phase-Shifted Full-Bridge DC/DC Converter

This paper presents a methodology to control a phase-shifted full-bridge (PSFB) dc/dc converter with variable switching frequency, as a function of the output load power. The main objective of such control is to maximize the conversion efficiency at a wide range of load power levels. By tuning the switching frequency, the net phase of the input impedance of the converter can be manipulated, and thus, at the lower load power operation, the net input impedance can be made highly inductive to achieve zero-voltage switching (ZVS) at the primary-side switches. This paper proposes an efficiency maximization method, which derives an optimum switching frequency based on the load power from a loss-minimization model. In addition, a state-feedback-based control method is proposed for maintaining a tight dynamic regulation over the converter output under a load transient. A 6-kW laboratory prototype of the PSFB converter is developed and designed to validate the proposed control algorithm. The experimental results show a conversion efficiency of 98% at full load and output voltage ripple of ±1%, while ensuring ZVS at all operating points between 100 W and 6 kW.

High-Efficiency Impedance Control Network Resonant DC–DC Converter With Optimized Startup Control

This paper presents an improved efficiency impedance control network (ICN) resonant dc–dc converter that maintains zero-voltage switching (ZVS) and near-zero-current switching (ZCS) across wide ranges in input and output voltages and output power. The improvement in efficiency in this burst mode operated converter is achieved through an optimized startup control that minimizes its startup transient and helps the converter maintain ZVS and near-ZCS operation, even during the startup for each burst cycle. This optimization of startup is made possible by a new accurate time domain model for the ICN converter waveforms that helps reduce the number of non-ZVS transitions by 75%. A prototype 200 W, 500 kHz ICN resonant converter designed to operate over an input voltage range of 25–40 V and output voltage range of 250–400 V is built and tested. The prototype ICN converter achieves a peak efficiency of 97.2% and maintains greater than 96.2% full power efficiency at 250 V output voltage across the nearly 2:1 input voltage range, and maintains full power efficiency above 94.6% across its full input and output voltage range. The converter also maintains efficiency above 93.6% over a 10:1 output power range across its full input and output voltage range.

High Performance Complementary Circuits Based on p-SnO and n-IGZO Thin-Film Transistors.

Oxide semiconductors are regarded as promising materials for large-area and/or flexible electronics. In this work, a ring oscillator based on n-type indium-gallium-zinc-oxide (IGZO) and p-type tin monoxide (SnO) is presented. The IGZO thin-film transistor (TFT) shows a linear mobility of 11.9 cm2/(V∙s) and a threshold voltage of 12.2 V. The SnO TFT exhibits a mobility of 0.51 cm2/(V∙s) and a threshold voltage of 20.1 V which is suitable for use with IGZO TFTs to form complementary circuits. At a supply voltage of 40 V, the complementary inverter shows a full output voltage swing and a gain of 24 with both TFTs having the same channel length/channel width ratio. The three-stage ring oscillator based on IGZO and SnO is able to operate at 2.63 kHz and the peak-to-peak oscillation amplitude reaches 36.1 V at a supply voltage of 40 V. The oxide-based complementary circuits, after further optimization of the operation voltage, may have wide applications in practical large-area flexible electronics.

High performance asymmetric V2O5-SnO2 nanopore battery by atomic layer deposition.

Here we report the high performance and cyclability of an asymmetric full cell nanopore battery, comprised of V2O5 as the cathode and prelithiated SnO2 as the anode, with integrated nanotubular Pt current collectors underneath each nanotubular storage electrode, confined within an anodized aluminium oxide (AAO) nanopore. Enabled by atomic layer deposition (ALD), this coaxial nanotube full cell is fully confined within a high aspect ratio nanopore (150 nm in diameter, 50 μm in length), with an ultra-small volume of about 1 fL. By controlling the amount of lithium ion prelithiated into the SnO2 anode, we can tune the full cell output voltage in the range of 0.3 V to 3 V. When tested as a massively parallel device (∼2 billion cm-2), this asymmetric nanopore battery array displays exceptional rate performance and cyclability: when cycled between 1 V and 3 V, capacity retention at the 200C rate is ∼73% of that at 1C, and at 25C rate only 2% capacity loss occurs after more than 500 charge/discharge cycles. With the increased full cell output potential, the asymmetric V2O5-SnO2 nanopore battery shows significantly improved energy and power density over the previously reported symmetric cell, 4.6 times higher volumetric energy and 5.2 times higher power density - an even more promising indication that controlled nanostructure designs employing nanoconfined environments with large electrode surface areas present promising directions for future battery technology.

High Performance Asymmetric V2O5-SnO2 Nanopore Battery By ALD

An array of nanobatteries, each self-aligned and fully confined within a single nanopore, provides an effective testbed for the rate performance and cyclability limits of nanostructured storage devices. With atomic layer deposition (ALD), we have previously synthesized and evaluated such structures in a symmetric configuration, comprised of nanotubular V2O5 electrodes as both anode and cathode and electrolyte confined within anodic aluminum oxide (AAO) nanopores. Each nanopore battery has ultra-small volume (~1fL) and shows superior performance when tested as massively parallel device (~2billion/cm2). [i] However, an asymmetric full cell configuration with a low voltage anode material has not been explored yet. Here we report an asymmetric full cell nanopore battery, comprised of V2O5 as cathode and prelithiated SnO2 as anode, with integrated nanotubular Pt current collectors underneath each nanotubular storage electrode. Also enabled by ALD, this coaxial nanotube full cell is fully confined within the high aspect ratio nanopore (150nm in diameter, 50um in length). By controlling the amount of lithium ion prelithiated into SnO2 anode, we can tune full cell output voltage in the range of 0.3V and 3V. This asymmetric nanopore battery array displays exceptional rate performance and cyclability. When cycled between 1V and 3V, it has capacity retention of approximately 73% at 200C rate compared to 1C, with only 2% capacity loss after more than 500 charge/discharge cycles. With increased full cell output potential, the asymmetric V2O5-SnO2 nanopore battery shows significantly improved energy and power density. This configuration presents a more realistic test - through its asymmetric (vs symmetric) configuration – of performance and cyclability in nanoconfined environment. [i] Liu, C.; Gillette, E. I.; Chen, X.; Pearse, A. J.; Kozen, A. C.; Schroeder, M. A.; Gregorczyk, K. E.; Lee, S. B.; Rubloff, G. W., An all-in-one nanopore battery array. Nature Nanotechnology 2014, 9 (12), 1031-1039.

Pulse width modulation technique for a three‐to‐five phase matrix converter with reduced commutations

Variable-speed multiphase drive systems have become an increasingly important topics compared with conventional three-phase one due to their distinct advantages. This study presents a new pulse width modulation (PWM) technique for controlling the three-to-five phase matrix converter to reduce the commutation number of the power switches and the total harmonic distortion, simultaneously. The proposed PWM technique provides full output voltage and frequency control in addition to unity input power factor by changing only five switch states during the control period. Moreover, it prevents direct switching or commutation between the maximum and minimum input voltages to reduce the switches voltage stress. Moreover, the proposed PWM technique provides output voltage ratio equal to 78.86% of the input voltage. The effectiveness of the proposed control scheme has been verified theoretically by using PSIM software and experimentally by using a laboratory prototype.

Low Power 10T XOR based 1 Bit Full Adder

The popularity and necessity of portable electronic systems by users have strongly influenced VLSI designers to make great effort for reduced silicon area, improved speeds, long duration battery life, and great reliability. The VLSI designers always try to save power consumption while designing a system. In this paer, an efficient methodology is presented to improve the output swing level of GDI gates. New designs of GDI based basic digital (AND, OR, XOR, XNOR) gates are presented using single pass transistors to improve swing level of GDI gates. The new design of basic gates with combination of GDI logic and pass transistor logic is called hybrid GDI technique. Compared to existing GDI technique with buffer restoration circuits, hybrid GDI implementation provides full swing output voltage in all digital circuits. Also it shows less power and less delay with about 60% area increase as compared to basic GDI.

Development of 600 kV triple resonance pulse transformer.

In this paper, a triple-resonance pulse transformer based on an air-core transformer is introduced. The voltage across the high-voltage winding of the air-core transformer is significantly less than the output voltage; instead, the full output voltage appears across the tuning inductor. The maximum ratio of peak load voltage to peak transformer voltage is 2.77 in theory. By analyzing pulse transformer's lossless circuit, the analytical expression for the output voltage and the characteristic equation of the triple-resonance circuit are presented. Design method for the triple-resonance pulse transformer (iterated simulation method) is presented, and a triple-resonance pulse transformer is developed based on the existing air-core transformer. The experimental results indicate that the maximum ratio of peak voltage across the load to peak voltage across the high-voltage winding of the air-core transformer is approximately 2.0 and the peak output voltage of the triple-resonance pulse transformer is approximately 600 kV.

High Overload Pressure Sensor Construct With Polysilicon Nanofilm

A high overload pressure sensor is prepared by surface micromachined technology, and its full scale pressure is 2.5 MPa. The structure of the proposed sensor is based on a seal cavity made by sacrificial layer, a deposition of polysilicon nanofilm acts as piezoresistors on the diaphragm. The stress distribution of the diaphragm of the sensor is simulated by the large displacement static analysis and the nonlinear contact analysis. Due to polysilicon high tensile strength and appropriate cavity height, the sensor full scale output voltage and overload capacity is greatly improved. The measured results indicate that the overpressure of the sensor sample is seven times higher than its full-scale pressure, and its full scale output voltage is 362 mV with a supply voltage of 5 V.

Impedance Control Network Resonant dc-dc Converter for Wide-Range High-Efficiency Operation

This paper introduces a new resonant converter architecture that utilizes multiple inverters and a lossless impedance control network (ICN) to maintain zero-voltage switching and near zero-current switching across wide operating ranges. Hence, the ICN converter is able to operate at fixed frequency and maintain high efficiency across wide ranges in input and output voltages and output power. The ICN converter architecture enables increase in switching frequency (hence reducing size and mass), while achieving very high efficiency. Three prototype 200-W 500-kHz ICN resonant converters, one with low-Q, one with medium-Q, and one with high-Q resonant tanks, designed to operate over an input voltage range of 25 to 40 V and an output voltage range of 250 to 400 V are built and tested. The low-Q prototype ICN converter achieves a peak efficiency of 97.1%, maintains greater than 96.4% full power efficiency at 250 V output voltage across the nearly 2:1 input voltage range, and maintains full power efficiency above 95% across its full input and output voltage range. It also maintains efficiency above 94.6% over a 10:1 output power range across its full input and output voltage range owing to the use of burst-mode control.

A Unified Phase-Shift Modulation for Optimized Synchronization of Parallel Resonant Inverters in High Frequency Power System

High frequency alternating current (HFAC) has already been applied in many power distribution systems due to outstanding merits. The circulation current control of the high frequency resonant inverter in parallel connection is more complicated than the low frequency counterpart. Methods from topology, modulation, and control perspectives have already been proposed; however, most of them are difficult to simultaneously accomplish the synchronization of magnitude and phase in high frequency circumstance. In this paper, a new modulation called as unified phase-shift modulation (PSM) is proposed to integrate the regulations of magnitude and phase. The unified PSM in steady state completely removes the modulation coupling between magnitude and phase so that the controllers of magnitude and phase can be independently accomplished without interactions. The operation scope of unified PSM is determined by zero voltage switching and total harmonic distortion of the resonant inverter. A prototype with two parallel inverters is established to verify the effectiveness with an operation frequency of 25 kHz and a full bridge output voltage of 40 V peak. The results of simulation and experiment prove that the unified PSM is superior over the existing PSM in HFAC circumstance. The controllers of magnitude and phase integrated by the proposed modulation can accomplish optimized output synchronization in the parallel single-stage resonant inverter.