Full Input Range Research Articles

Correlated Double Amplifying Readout Technique for Low-Noise Power-Efficient MEMS Capacitive Accelerometer

MEMS capacitive accelerometer for the Internet of things applications is designed with open-loop structure rather than close-loop structure to achieve low power consumption. In the open-loop structure, voltage control readout structure instead of charge control readout structure is preferred for low cost. However, the voltage control readout structure suffers from low power efficiency (in terms of <i>FoM</i>) due to significant parasitic-capacitance-induced noise. In this paper, the correlated double amplifying (CDA) technique is proposed to reduce the noise of the voltage control readout circuit with high power efficiency. Although, traditional correlated double sampling (CDS) technique can also be used in readout circuit to reduce the parasitic-capacitance-induced noise, it sacrifices driving ability and bandwidth of the readout circuit while CDA does not. The CDA technique adopts correlated amplifying to reduced noise without significant increase of power consumption. Thus, CDA technique leads to higher power efficiency. The CDA technique is demonstrated in a fully-differential readout circuit fabricated in a 0.18um CMOS process and tested with a sensing element from a commercial MEMS accelerometer. The measurement results show that noise floor of the readout circuit is 0.5<i>aF</i>/&#x221A;<i>Hz</i> and the noise floor of the whole system is 112<i>ug</i>/&#x221A;<i>Hz</i>, with a power consumption of 139&#x03BC;W and a bandwidth of 12.5kHz. The full input range is &#x00B1;4g, a <i>FoM</i>₁ of 80<i>pJ</i> and a <i>FoM</i>₂ of 254<i>uW</i> &#x2219; <i>ug</i>/<i>Hz</i> are achieved.

A 12-Bit Time-Interleaved 400-MS/s Pipelined ADC With Split-ADC Digital Background Calibration in 4,000 Conversions/Channel

Split analog-to-digital converter (ADC) digital background calibration with full-input-range error detection schemes is proposed to rapidly correct the gain and nonlinearity errors in the multi-bit first stage of a multi-channel time-interleaved (TI) pipelined ADC. By adding a vertical shift between the residue transfer curves of the first stages in two half-ADCs which are split from a single ADC, the error detection schemes of the proposed calibration are effective in the full-input range. The larger error detection range means that calibration is activated more often, resulting in fewer ADC conversions to converge. In addition, the designed fast-settling switch controller enables a 12-bit resistor-ladder DAC (R-DAC) for high-speed application. Furthermore, by applying the proposed calibration and sharing the R-DAC among all channels, the need for gain mismatch calibration between interleaved channels is eliminated. Consequently, the calibration time and complexity are further reduced. A 12-bit 400-MS/s 4-channel TI pipelined ADC prototype is implemented in 40-nm CMOS technology with an active area of 0.71 mm2, the measured SNDR and INL of which are improved up to 23 dB and 96 LSB via the proposed calibration. Compared with prior-art ADCs using background calibration, the proposed ADC achieves the fastest background calibration in 4,000 conversions/channel, which is at least $5{\times }$ less than the others.

Influence of LFSR Dither on the Periods of a MASH Digital Delta–Sigma Modulator

This brief shows that applying a linear feedback shift register (LFSR) dither to a digital delta–sigma modulator (DDSM) cannot always increase its fundamental period. For some DDSMs, the LFSR dither may reduce its period in some cases, instead of increasing it, which worsens the output spectrum. Hence, this brief calculates the dithered DDSM’s period and analyzes the influence of LFSR dither on the period. Furthermore, for this kind of DDSM, this brief explains how to add the LFSR dither to increase the period for a full input range. Finally, the experiment is performed to confirm the analysis.

Research on the LLC Resonant Converter Based on SiC Device in the Auxiliary Converter of Subway

In this paper, the LLC resonant converter based on SiC devices is applied to the auxiliary converter of subway. The principle of operation of this converter is analyzed in detail, and a LLC resonant converter with a capacity of 40kW is designed. By building the system circuit in the PSIM simulation software, it is proved that the converter can work normally, the ZVS of the switches and the ZCS of the rectifier diodes are realized in the full input range and the full load range to ensure the high-efficiency operation of the circuit under high frequency conditions and meet the requirements of auxiliary converter in subway.

Notice of Violation of IEEE Publication Principles: Design of Monolithic Low Dropout Regulator for Wireless Powered Brain Cortical Implants Using a Line Ripple Rejection Technique

This brief introduces an integrated low dropout regulator for wireless powered brain cortical implants. A line ripple rejection technique is employed to improve the line regulation of the regulator. A fast transient response is ensured to accommodate frequent changes of workload and power. The system is stabilized over the entire load range without using any external compensation capacitors. System modeling and theoretical analysis are conducted to offer a systematic study on the proposed structure. The regulator was fabricated with an IBM 130-nm CMOS process. The active die area is 0.025 mm2. Experimental results show that the power supply rejection ratio remains above 52.8 dB within the interested frequency band. The line regulation is controlled below 0.44% throughout the full input range. The output voltage can recover within 69 ns from a full load current change, with a less than 8.1-mV voltage droop.

Spur-Free MASH Delta-Sigma Modulation

For multistage noise-shaping (MASH) delta-sigma modulation, this paper presents a new structure that is free of spurs for all input values. The proposed MASH structure cascades several first-order delta-sigma modulators (DSMs) like the traditional MASH structure but has an additional feedforward connection between two adjacent stages. The proposed MASH structure can increase the sequence length and thus reduce spurs. The reason why the proposed MASH structure has a long sequence length for the full input range is mathematically proved, and simulations are performed to verify the effect of the long sequence length. Simulation results show that the performance of the proposed MASH structure is close to that of the ideal DSM. In addition, the proposed MASH structure requires almost the same hardware cost as the traditional MASH structure.

A NEW MODELING METHOD OF VERTICAL ELECTROSTATIC COMB DRIVE

International Journal of Computational Engineering ScienceVol. 04, No. 03, pp. 641-644 (2003) Poster PapersNo AccessA NEW MODELING METHOD OF VERTICAL ELECTROSTATIC COMB DRIVEJ. C. Chiou and Y. J. LinJ. C. ChiouDepartment of Electrical and Control Engineering, National Chiao Tung University, Hsin-Chu, Taiwan, R.O.C. Search for more papers by this author and Y. J. LinDepartment of Electrical and Control Engineering, National Chiao Tung University, Hsin-Chu, Taiwan, R.O.C. Search for more papers by this author https://doi.org/10.1142/S1465876303001940Cited by:2 PreviousNext AboutSectionsPDF/EPUB ToolsAdd to favoritesDownload CitationsTrack CitationsRecommend to Library ShareShare onFacebookTwitterLinked InRedditEmail AbstractIn this paper, we have successfully modeling a vertical motion electrostaitc comb drive and proof it's efficiency by using existed experimental data. A commercial 3-D MEMS Simulator was employed to stimulate the static levitation of vertical comb drive. Note that, by gradually increasing the dc bias voltage, each simulation process is either converged slowly or even enters the divergence stage. Hence, the 3-D simulator is degraded in simulating vertical electrostatic comb drive in full input range. In the present modelling method, Maxwell 2-D solver was employed to calculate the comb finger capacitance at different z positions firstly. Second, A 6th-order curve fitting was used to extract the capacitance function, C(z), and the unit electrostastic force function, dC/dz, was obtained by taking derivative of capacitance function. Finally, a dynamic system model block diagram was established in Matlab Simulink program environment. A set of ideal geometry parameter was selected to verify the accuracy of our model. The simulation results were compared with the experiment results, and a 50% error was observed. After replaces the ideal geometry parameters with actual geometry parameters, the error was reduced substantially, within 10%.Keywords:vertical comb drivelevitationmodelingMEMS simulationconvergence References IntelliSuite Windows Version User Documentation. Version 10. Corning IntelliSense Inc., Wilmington, MA 01887 . Google ScholarH. Yie, X. Cai and J. White, Numerical Modeling of Processes and Devices for Integrated Circuits, 1994 (International Workshop, 1994) pp. 137–140. Crossref, Google ScholarW. C. Tang, M. G. Lim and R. T. Howe, IEEE JNL. Of MEMS 1(4), 170 (1992). Crossref, Google ScholarH. Xie and G. K. Fedder, Sensors and Actuators A95, 212 (2002). Google Scholar H. H. Bau and N. F. deRooij , Sensors a comprehensive survey: Volume 7: Mechanical Sensors ( Weinheim , 1994 ) . Google Scholar FiguresReferencesRelatedDetailsCited By 2A Micromirror With Large Static Rotation and Vertical ActuationJin-Chern Chiou, Chin-Fu Kou and Yung-Jiun Lin1 Mar 2007 | IEEE Journal of Selected Topics in Quantum Electronics, Vol. 13, No. 2MEMS-based miniature optical pickup Yi Chiu, Cheng-Huan Chen, Jin-Chern Chiou, Weileun Fang and H.-P.D. Shieh1 Feb 2005 | IEEE Transactions on Magnetics, Vol. 41, No. 2 Recommended Vol. 04, No. 03 Metrics History Keywordsvertical comb drivelevitationmodelingMEMS simulationconvergencePDF download

Aperiodic stochastic resonance in a hysteretic population of cardiac neurons.

Aperiodic stochastic resonance (ASR) is studied for a densely interconnected population of excitatory and inhibitory neurons that exhibit hysteresis. Switching between states in the presence of noisy external forcing is represented as a "competition between averages" and this is further explained through a semianalytical model. In contrast to energy-based approaches where only the timing of a switch between states is represented, the competition between averages also identifies the input history responsible for a switch. This last point leads to some interesting conclusions regarding cause and effect in the presence of noisy forcing of a hysteretic system. For example, at subthreshold inputs, it is found that the input history causing a switch between states is primarily dependent upon the noise level even though the corresponding time to switch is sensitive to both the distance from the threshold and the noise level. Since the application considered here is to cardiac neuronal control, control performance is considered over the full input range. Noise tuning for adequate control performance is found to be unnecessary if the noise level is high enough. This is consistent with studies of ASR for sensory neurons. Another observation made here that may be of clinical significance is that at higher noise levels, constraints placed upon inputs to ensure adequate control performance are likely to depend upon the switching direction.

Concept for aelf-calibrating floatingpoint-converter for audio-applications

The basic concept of the converter grew out of the problems that result from the use of standard linear 16-bit converters in audio-engineering. This type of converter achieves good quality, if the full input range is used by the signal (signal to noise ratio is theoretically SNR = 96 dB). But with decreasing amplitude there is a linear decrease with the signal. With the use of faster converters and oversampling methods, it is possible to improve the quality, but the basic characteristic of the ratio SNR versus signal-amplitude remains unchanged. In the past, a method to cope with this problem was the construction of floating-point-converters or converters with non-linear characteristics. For today's quality standard, this methods cannot be applied in the original form, because the different gain-ratios or non-linear characteristics cannot be reproduced as exactly as necessary. The concept presented combines the model of a floating point converter with a self-calibrating mechanism to correct the gain-ratios with a digital signal processor. In order to demonstrate the principle, a 16-bit-converter and a 9-amplifier-chain with gain-steps of 2 was used. But it is obvious that other configurations can also be used, especially, if the concept is further combined with an oversampling method.