Full Hardware Implementation Research Articles

Full hardware implementation of neuromorphic visual system based on multimodal optoelectronic resistive memory arrays for versatile image processing

In-sensor and near-sensor computing are becoming the next-generation computing paradigm for high-density and low-power sensory processing. To fulfil a high-density and efficient neuromorphic visual system with fully hierarchical emulation of the retina and visual cortex, emerging multimodal neuromorphic devices for multi-stage processing and a fully hardware-implemented system with versatile image processing functions are still lacking and highly desirable. Here we demonstrate an emerging multimodal-multifunctional resistive random-access memory (RRAM) device array based on modified silk fibroin protein (MSFP), exhibiting both optoelectronic RRAM (ORRAM) mode featured by unique negative and positive photoconductance memory and electrical RRAM (ERRAM) mode featured by analogue resistive switching. A full hardware implementation of the artificial visual system with versatile image processing functions is realised for the first time, including ORRAM mode array for the in-sensor image pre-processing (contrast enhancement, background denoising, feature extraction) and ERRAM mode array for near-sensor high-level image recognition, which hugely improves the integration density, and simply the circuit design and the fabrication and integration complexity.

Streamlined NTRU Prime on FPGA

We present a novel full hardware implementation of Streamlined NTRU Prime, with two variants: a high-speed, high-area implementation and a slower, low-area implementation. We introduce several new techniques that improve performance, including a batch inversion for key generation, a high-speed schoolbook polynomial multiplier, an NTT polynomial multiplier combined with a CRT map, a new DSP-free modular reduction method, a high-speed radix sorting module, and new encoders and decoders. With the high-speed design, we achieve the to-date fastest speeds for Streamlined NTRU Prime, with speeds of 5007, 10,989, and 64,026 cycles for encapsulation, decapsulation, and key generation, respectively, while running at 285 MHz on a Xilinx Zynq Ultrascale+. The entire design uses 40,060 LUT, 26,384 flip-flops, 36.5 Bram, and 31 DSP.

A Fast, Energy Efficient and Tunable Magnetic Tunnel Junction Based Bitstream Generator for Stochastic Computing

This paper presents a full hardware implementation of a magnetic tunnel junction based stochastic tunable bitstream generator. It provides highly accurate control of the switching probability, while showing important robustness to process and temperature variations. We propose a new architecture of sensing scheme based on the pre-charged sense amplifier approach that uses an asynchronous digital module to control the internal signals of the sense amplifier with the purpose of improving the reliability against the timing hazards and reducing the power consumption by detecting the end of the reading to stop the required static currents. The circuit also features a digital feedback loop that analyzes the output bitstream and adapt the current in such a way that the bitstream encodes precisely the required probability. This circuit features an important bit generation rate at a low energy cost. Based on an exhaustive characterization of the circuit, we provide a behavioral description in Verilog, with timing and power files to be integrated as a standard cell in the digital design flow for application level evaluation of the performance. Thus, we also provide a design and evaluation flow from device to digital level of abstraction.

Embedded Real-Time Simulator for Sensorless Control of Modular Multi-Level Converters

This paper suggests the application of an embedded real-time simulator (eRTS) in the context of voltage–sensorless control of a modular multilevel power converter (MMC). This eRTS acts as an observer and ensures digital redundancy in the case of any fault occurring among the capacitor voltage sensors of the MMC submodules. Hence, in such a faulty situation, the MMC controller switches from the measured voltages to their estimated counterparts. As for the digital implementation, to ensure a high level of integration of the overall control system, the Xilinx Zynq-7020 system-on-chip field programmable gate array (SoC-FPGA) device was used. The controller was implemented in the hardwired ARM Cortex-A9 processor, with a 100 µs time step. Regarding the time-sensitive blocks (PWM, eRTS and measurements filtering), a full hardware implementation was privileged, using the FPGA fabric. The execution time of these blocks was 710 ns with a 100 MHz system clock, and the synchronization with the analog to digital acquisition chain was made with a 5 µs time resolution. The whole proof-of-concept system was experimentally tested, including the time/area evaluation of the implemented designs and the experimental validation of the eRTS estimations in both healthy and faulty scenarios.

An Efficient Full Hardware Implementation of Extended Merkle Signature Scheme

This paper presents a full hardware implementation of the eXtended Merkle Signature Scheme (XMSS), a NIST approved and IETF RFC specified post-quantum cryptography (PQC) algorithm. An optimized node traversal is proposed to enable efficient memory utilization without compromising the computational latency of the L-tree and Merkle tree construction, which are two key components used for the compression of the Winternitz One-Time Signature (WOTS) public key in XMSS. The computation of the authentication path during signature generation has also been significantly sped up by our proposed hardware implementation of the Buchmann, Dahmen, and Schneider (BDS) algorithm. Our implementation has completely avoided the use of block random-access memory, which is known to be vulnerable to side-channel attacks. The memory requirement has been highly optimized for implementation with small flip-flop chains and register counters as pointers for fast data access. To the best of our knowledge, this is the first full hardware implementation of all three <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">key generation</i> , <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">signing</i> and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">verification</i> operations of XMSS. The design has been prototyped and evaluated on a 28 nm FPGA platform to demonstrate its performance improvements over the most efficient software and hardware/software co-design methods reported to date. Specifically, it increases the computational efficiency of the best reported XMSS implementation for <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">key generation</i> and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">signature generation</i> by about 20% and 50%, respectively. It can also run at 10% higher clock speed than the fastest hardware implementation of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">signature verification</i> in FPGA with 8% lower hardware resource utilization.

FPGA Hardware in the Loop Validation of Asynchronous Machine with Full Direct Torque Control Implementation

This article provides a full hardware implementation for direct torque control (DTC) of an asynchronous motor (AM) on the Field Programmable Gate Array (FPGA). Due to its high processing frequency, the FPGA circuit presents an alternative for achieving a high performance DTC implementation. This cannot be achieved by any DSP or microcontroller application. The proposed hardware architecture implements three components of DTC control strategy (the integral proportional speed regulator, the estimation and the switching blocks). This implementation has the advantage of being faster, more efficient and with minimum hardware resources on the target FPGA board. The hardware architecture of the DTC control was designed and simulated in Matlab / Simulink using XSG blocks, then synthesized with the Xilinx ISE 14.2 tool, implemented and validated on the Xilinx Virtex-4 FPGA circuit by Hardware in the Loop process.

Energy-efficient Mott activation neuron for full-hardware implementation of neural networks.

To circumvent the von Neumann bottleneck, substantial progress has been made towards in-memory computing with synaptic devices. However, compact nanodevices implementing non-linear activation functions are required for efficient full-hardware implementation of deep neural networks. Here, we present an energy-efficient and compact Mott activation neuron based on vanadium dioxide and its successful integration with a conductive bridge random access memory (CBRAM) crossbar array in hardware. The Mott activation neuron implements the rectified linear unit function in the analogue domain. The neuron devices consume substantially less energy and occupy two orders of magnitude smaller area than those of analogue complementary metal-oxide semiconductor implementations. The LeNet-5 network with Mott activation neurons achieves 98.38% accuracy on the MNIST dataset, close to the ideal software accuracy. We perform large-scale image edge detection using the Mott activation neurons integrated with a CBRAM crossbar array. Our findings provide a solution towards large-scale, highly parallel and energy-efficient in-memory computing systems for neural networks.

A serial high-speed satellite communication CODEC: Design and implementation of a SpaceFibre interface

In the last few years, satellite on-board data handling bandwidth requirements grew significantly, as well as production volume of these systems. A series of different protocols currently try to answer this need. In particular, the European Space Agency developed an open protocol solution: SpaceFibre. The SpaceFibre protocol can sustain a line rate of 6.25 Gb/s per lane (up to 16 lanes). It offers advanced and flexible Quality-of-Service features, as well as Fault Detection Isolation and Recovery services. The protocol structure has been developed so that full hardware implementation of its core layers is straightforward, granting high performances at low price in terms of complexity and power consumption, one of the most stringent requirements in space applications. In this paper, a FPGA implementation on both rad-hardened (RTAX2000, RTG4, Virtex-5) and commercial (ZYNQ 7000) devices of the SpaceFibre CODEC is presented together with its verification environment and a hardware validation set-up. Particular attention is given to the trade-off between resources utilisation, power consumption and CODEC configurations, in order to enable future system adopters to efficiently explore the design space.

A novel memristive true random number generator design

PurposeIn this work, a true random number generator is designed by sampling the double-scroll analog continuous-time chaotic circuit signals.MethodologyA Chua circuit based on memristance simulator is designed to obtain a non-linear term for a chaotic dynamic system. It is implemented on the board by using commercially available integrated circuits and passive elements. A low precision ADC which is commonly found in the market is used to sample the chaotic signals. The mathematical analysis of the chaotic circuit is verified by experimental results.OriginalityIt is aimed to be one of the pioneering studies (including low precision ADC) in the literature on the implementation of memristive chaotic random number generators.FindingsTwo new methods are proposed for post-processing and creating random bit array using XOR operator and J-K flip flop. The bit stream obtained by a full-hardware implementation successfully passed the NIST-800-22 test. In this respect, the availability of the memristance simulator circuit, memristive chaotic double-scroll attractor, proposed random bit algorithm and the randomness of the memristive analog continuous-time chaotic true number generator were also verified.

An Energy-Efficient Reconfigurable DTLS Cryptographic Engine for Securing Internet-of-Things Applications

This paper presents the first hardware implementation of the Datagram Transport Layer Security (DTLS) protocol to enable end-to-end security for the Internet of Things (IoT). A key component of this design is a reconfigurable prime field elliptic curve cryptography (ECC) accelerator, which is 238x and 9x more energy-efficient compared to software and state-of-the-art hardware respectively. Our full hardware implementation of the DTLS 1.3 protocol provides 438x improvement in energy-efficiency over software, along with code size and data memory usage as low as 8 KB and 3 KB respectively. The cryptographic accelerators are coupled with an on-chip low-power RISC-V processor to benchmark applications beyond DTLS with up to two orders of magnitude energy savings. The test chip, fabricated in 65 nm CMOS, demonstrates hardware-accelerated DTLS sessions while consuming 44.08 uJ per handshake, and 0.89 nJ per byte of encrypted data at 16 MHz and 0.8 V.

A Hardware Implementation for Colour Edge Detection Using Prewitt-Inspired Filters Based on Geometric Algebra

Geometric algebra (GA) is a powerful mathematical tool that offers intuitive solutions for image-processing problems, including colour edge detection. Rotor-based and Prewitt-inspired Sangwine (RBS and PIS) filters are amongst the efficient algorithms based on GA operators for solving colour edge detection problem. Algorithms in GA framework have enormous computational load that limits the general-purpose processors’ ability to execute them in reasonable time. Recently, some specialized hardware architectures, called full-hardware implementations, are proposed. These architectures, such as ConformalALU co-processor, are able to execute GA algorithms in acceptable time with the moderate use of computational resources. So far, all colour edge detection hardwares in GA framework exploited RBS filters. Nevertheless, this novel work presents a full-hardware architecture for efficient execution of PIS filters. PIS filters consume less computational resources and are faster to execute. For comparison, the hardware obtained by Gaalop pre-compiler uses twice as much resources with the same speed as the proposed hardware. As an evidence of faster operation, the proposed hardware is able to execute the edge detection algorithm almost 315 times faster than a GA co-processor, with only 2.5 times of its resources.

Adaptive learning rule for hardware-based deep neural networks using electronic synapse devices

In this paper, we propose a learning rule based on a back-propagation (BP) algorithm that can be applied to a hardware-based deep neural network (HW-DNN) using electronic devices that exhibit discrete and limited conductance characteristics. This adaptive learning rule, which enables forward, backward propagation, as well as weight updates in hardware, is helpful during the implementation of power-efficient and high-speed deep neural networks. In simulations using a three-layer perceptron network, we evaluate the learning performance according to various conductance responses of electronic synapse devices and weight-updating methods. It is shown that the learning accuracy is comparable to that obtained when using a software-based BP algorithm when the electronic synapse device has a linear conductance response with a high dynamic range. Furthermore, the proposed unidirectional weight-updating method is suitable for electronic synapse devices which have nonlinear and finite conductance responses. Because this weight-updating method can compensate the demerit of asymmetric weight updates, we can obtain better accuracy compared to other methods. This adaptive learning rule, which can be applied to full hardware implementation, can also compensate the degradation of learning accuracy due to the probable device-to-device variation in an actual electronic synapse device.

A flexible VHF-band aeronautical datalink receiver based on software defined radio

The primary objective of the project was to acquaint ourselves with software defined radio (SDR) techniques to put into action some of the concepts covered during digital communications courses. SDR offers an easy way to design and implement flexible radiofrequency (RF) transceiver architectures using mainly software developments [1]. Thus, it allows to get promptly familiar with classic issues to overcome when designing receivers (RF electronics impairments, asynchronously-sampled signals...) without getting restricted by material constraints traditionally brought by full-hardware implementations (i.e., cost of hardware components to be soldered together, need of various development and testing instruments...).

An Efficient Digital Background Control for Hybrid Transformer-Based Receivers

The design and hardware implementation of a digital control system tailored to a hybrid transformer-based duplexer is proposed. Working at Nyquist sampling frequency, it finds the optimal transmit-receive isolation in about 150 $\mu \text{s}$ even when modulated signals with high PAPR (16-QAM) are transmitted. A simple tracking algorithm, operating in background, preserves this condition over time. Uninterrupted system operation can be guaranteed through an auxiliary receiver with sub-mW power dissipation, minimizing the overhead of the entire control system. The algorithms are implemented on FPGA to carry out the experimental validation of the full hardware implementation. Moreover, the hardware overhead of the digital control algorithm is analyzed, synthesizing the digital circuit in 40-nm CMOS technology.

Comparing three online evolvable hardware implementations of a classification system

In this paper, we present three implementations of an online evolvable hardware classifier of sonar signals on a 28 nm process technology FPGA, and compare their features using the most relevant metrics in the design of hardware: area, timing, power consumption, energy consumption, and performance. The three implementations are: one full-hardware implementation in which all the modules of the evolvable hardware system, the evaluation module and the Evolutionary Algorithm have been implemented on the ZedBoard™ Zynq® Evaluation Kit (XC7-Z020 ELQ484-1); and two hardware/software implementations in which the Evolutionary Algorithm has been implemented in software and run on two different processors: Zynq® XC7-Z020 and MicroBlaze™. Additionally, each processor-based implementation has been tested at several processor speeds. The results prove that the full-hardware implementation always performs better than the hardware/software implementations by a considerable margin: up to $$\times \,7.74$$ faster than MicroBlaze, between $$\times \,1.39$$ and $$\times \,2.11$$ faster that Zynq, and $$\times \,0.198$$ lower power consumption. However, the hardware/software implementations have the advantage of being more flexible for testing different options during the design phase. These figures can be used as a guideline to determine the best use for each kind of implementation.

Design and Implementation of Real Time Noise Cancellation System based on Spectral Subtraction Method

Abstract In this paper, a real-time digital signal noise cancellation system is designed based on Spectral Subtraction Method. The system cancels the noise in frequency domain by estimating the noise energy spectral from a noisy input. Since that method is performed in frequency domain with polar form, a time to frequency domain and rectangular to polar transformer with each of their complement circuits are needed to perform the noise cancellation operation. Considering high speed computation with lower system frequency for a real-time processing and low power consumption, an FPGA based full-hardware implementation is used in proposed system. As a result, the proposed noise cancellation system implementation result is able to perform a real time noise cancellation with the SNR value of 71 dB and use about 47,000 FPGA logic elements with 32 bits data resolution.

Optimal hardware/software partitioning of a system on chip FPGA-based sensorless AC drive current controller

The recent field programmable gate array (FPGA) system on chip devices offer a new degree of design freedom. Indeed, these digital components allow the combination of software treatment (by the on-chip processor cores) and hardware treatment (hardware architecture made by the interconnection of the FPGA logic cells). In the field of industrial control applications, this digital technology is appropriate to reach an optimum between the control performances, the controller algorithm complexity and the design flexibility. On the other hand, a co-design methodology is necessary to make an efficient partitioning of the control algorithm so as to define modules to be software-made and modules to be hardware-made.To this aim, this paper deals with a co-design methodology adapted to SoC FPGA-based controllers for embedded power applications. The case study is a sensorless current controller of a synchronous machine using an extended Kalman filter (EKF). This co-design development is based on two reference implementations: a full software implementation and a full hardware implementation that are also discussed. To find the optimal HW/SW partitioning, a non-dominated sorting genetic algorithm (NSGA-II) is used.

Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation

Discrete microprocessor-based equipment is a typical synchronization system on the market which implements the most critical features of the synchronization protocols in hardware and the synchronization algorithms in software. In this paper, a new clock discipline algorithm for hardware implementation is presented, allowing for full hardware implementation of synchronization systems. Measurements on field-programmable gate array prototypes show a fast convergence time (below 10 s) and a high accuracy (1 μs ) for typical configuration parameters.

An Improved Color-based Particle Filter and Its Full Hardware Implementation

传统基于颜色的粒子滤波算法在硬件实现中存在着跟踪效果不理想、实时性差等问题。该文结合硬件电路需要对基于颜色的粒子滤波算法进行了改进，在传统SR重采样算法的基础上将剩余粒子撒向目标点附近，以提高其在硬件环境下跟踪的准确性与稳定性。文中给出了改进算法的全硬件实现的电路架构，并在FPGA上完成了目标跟踪系统的实现。实验表明提出改进算法与硬件实现方案对简单背景环境下运动目标有着良好的跟踪效果，系统实时处理能力可达72 FPS，而硬件消耗为7387个逻辑单元。为进一步适应复杂的应用环境，在此粒子滤波器基础上给出了可扩展的分布式粒子滤波系统的架构以及相应的重采样策略，良好的并行性与可扩展性使得系统能够完成复杂背景环境下多特征、多目标的跟踪任务。

Fully hardware based WFQ architecture for high-speed QoS packet scheduling

A full hardware implementation of a Weighted Fair Queuing (WFQ) packet scheduler is proposed. The circuit architecture presented has been implemented using Altera Stratix II FPGA technology, utilizing Reduced Latency DRAM (RLDRAM) II and Quad Data Rate (QDR) II SRAM memory components. The circuit can provide fine granularity Quality of Service (QoS) support at a line throughput rate of 12.8 Gb/s in its current implementation. The authors suggest that, due to the flexible and scalable modular circuit design approach used, the current circuit architecture can be targeted for a full ASIC implementation to deliver 50 Gb/s throughput. The circuit itself comprises three main components; a WFQ algorithm computation circuit, a tag/time-stamp sort and retrieval circuit, and a high throughput shared buffer. The circuit targets the support of emerging wireline and wireless network nodes that focus on Service Level Agreements (SLA's) and Quality of Experience.