Full-duplex Transceiver Research Articles

Spectral Efficient Cognitive Radio Transmission using Full Duplex Communication

Background/Objectives: The rapid growth of demand for ever-increasing data rate and wireless services results in spectrum scarcity. Cognitive radio technology is used as solution for this problem. Methods/Statistical Analysis: Spectrum sensing is the key mechanism used to share the spectrum in cognitive radio which will solve the spectrum scarcity problem. Conventional cognitive radio is operated in half-duplex mode which fist sense the spectrum hole and transmit if spectrum hole is found. This listen and talk approach has the constraint of losing transmission opportunities during sensing or has the Risk of undetectable collisions during transmission. This problem can be rectified by operating the cognitive radio in full duplex mode. Findings: Modern full-duplex wireless radio transceivers will be capable of simultaneous spectrum sensing and transmission. But one of the main issues in the full duplex simultaneous sensing and transmission is the residual self-interference.In this paper a full duplex cognitive radio with two antennas (2x2 MIMO) which will provide for higher physical isolation is proposed with the self-interference cancelling technique. The technique consists of a power control and interference cancellation filter or self-interference whitening filter. Since the full-duplex system, radios transmit and sense simultaneously in the same frequency band at the same time, providing improvement in spectral efficiency over a half-duplex system. Applications/Improvements: The result shows that the proposed full duplex cognitive radio provides spectral efficiency of 5.2 bits/Hz/sec at 11dB SNR but the conventional half duplex cognitive radio provides only 2 bits/Hz/sec.

An Efficient Two-Step Power Allocation Method for OFDM-Based Two-Way Full-Duplex Links

An efficient two-step method to allocate power for orthogonal frequency division multiplexing-based full-duplex (FD) two-way communication links is proposed in this letter. We try to maximize sum data rate of the two-way link by allocating available power over each subcarrier at both FD transceivers with imperfect self-interference cancellation. This sum-rate optimization problem is formulated under total power constraint. In order to solve this problem, we first consider a one-subcarrier problem and derive the closed-form solution for power allocation. Based on this result, the multi-carrier optimization problem can be solved by our proposed two-step method. First, we allocate total power to each subcarrier optimally, and then we solve the power allocation problem for each subcarrier. Compared with direct dual decomposition method, numerical results indicate that our two-step method can obtain the same two-way link performance, however, with much lower computational complexity.

Relay Opportunistic Spectrum Sharing Based on the Full‐Duplex Transceiver

Opportunistic spectrum sharing (OSS) and cooperative spectrum sharing (CSS) are typical dynamic spectrum accessing (DSA) technologies to effectively improve spectrum efficiency (SE) and energy efficiency (EE). However, OSS provides no benefit to the primary user, whereas CSS, although simultaneously improving SE of the primary user and the secondary user, needs a proper cooperative mechanism with negotiation cost. To overcome these drawbacks, two kinds of relay OSS (ROSS) models are proposed to maximize SE and EE, respectively. When full-duplex transceiver is adopted by the secondary user, the proposed ROSS models can simultaneously improve the performance of both the primary user and the secondary user without requiring any negotiation. To make the study more complete, we consider both perfect channel state information (CSI) and imperfect CSI scenarios. Numerical results demonstrate the effectiveness of the proposed models and show that the performance of both the primary user and the secondary user can be improved under ROSS models.

A Single-Chip Full-Duplex High Speed Transceiver for Multi-Site Stimulating and Recording Neural Implants.

We present a novel, fully-integrated, low-power full-duplex transceiver (FDT) to support high-density and bidirectional neural interfacing applications (high-channel count stimulating and recording) with asymmetric data rates: higher rates are required for recording (uplink signals) than stimulation (downlink signals). The transmitter (TX) and receiver (RX) share a single antenna to reduce implant size and complexity. The TX uses impulse radio ultra-wide band (IR-UWB) based on an edge combining approach, and the RX uses a novel 2.4-GHz on-off keying (OOK) receiver. Proper isolation (>20 dB) between the TX and RX path is implemented 1) by shaping the transmitted pulses to fall within the unregulated UWB spectrum (3.1-7 GHz), and 2) by space-efficient filtering (avoiding a circulator or diplexer) of the downlink OOK spectrum in the RX low-noise amplifier. The UWB 3.1-7 GHz transmitter can use either OOK or binary phase shift keying (BPSK) modulation schemes. The proposed FDT provides dual band 500-Mbps TX uplink data rate and 100 Mbps RX downlink data rate, and it is fully integrated into standard TSMC 0.18- μm CMOS within a total size of 0.8 mm(2). The total measured power consumption is 10.4 mW in full duplex mode (5 mW at 100 Mbps for RX, and 5.4 mW at 500 Mbps or 10.8 pJ/bit for TX). Additionally, a 3-coil inductive link along with on-chip power management circuits allows to powering up the implantable transceiver wirelessly by delivering 25 mW extracted from a 13.56-MHz carrier signal, at a total efficiency of 41.6%.

Electrical balance duplexing for small form factor realization of in-band full duplex

Transceiver architectures utilizing various self-interference suppression techniques have enabled simultaneous transmission and reception at the same frequency. This full-duplex wireless offers the potential for a doubling of spectral efficiency; however, the requirement for high transmit-to-receive isolation presents formidable challenges for the designers of full duplex transceivers. Electrical balance in hybrid junctions has been shown to provide high transmit- to-receive isolation over significant bandwidths. Electrical balance duplexers require just one antenna, and can be implemented on-chip, making this an attractive technology for small form factor devices. However, the transmit-to-receive isolation is sensitive to antenna impedance variation in both the frequency domain and time domain, limiting the isolation bandwidth and requiring dynamic adaptation. Various contributions concerning the implementation and performance of electrical balance duplexers are reviewed and compared, and novel measurements and simulations are presented. Results demonstrate the degradation in duplexer isolation due to imperfect system adaptation in user interaction scenarios, and requirements for the duplexer adaptation system are discussed.

Real-Time Adaptive Transmitter Leakage Cancelling in 5.8-GHz Full-Duplex Transceivers

This paper describes the design principles for a real-time adaptive transmitter leakage canceller and introduces its training algorithm for fast adaptation. The canceller implements the active feed-forward analog cancelling technique, which considers the injection at the receiving input of the self-interfering antiphase signal. An extensive characterization carried out on a prototype designed to operate at the center frequency of 5.8 GHz demonstrates the performance of the prototype in term of cancellation and tracking convergence speed, and confirms the validity of the canceller design principles. Measurements at 5.8 GHz show that for isolation between the transmitting and receiving antenna up to 35 dB with arbitrary phase, an isolation above 60 dB is obtained in 98.5% of the tests and this result is reached in six steps. When applied to a wireless transceiver for electronic-toll collection system operating in full duplex at 5.8 GHz under regulation European Telecommunications Standards Institute ES200674, the prototype permits a signal-to-noise-ratio enhancement of 8.3 dB.

A 0.87 W Transceiver IC for 100 Gigabit Ethernet in 40 nm CMOS

This paper describes a low-power 100 Gigabit Ethernet transceiver IC compliant with IEEE802.3ba 100GBASE-LR4 in 40 nm CMOS. The proposed bidirectional full-duplex transceiver IC contains a total of eight 28 Gb/s CDRs. Each CDR lane incorporates phase-rotator-based delay- and phase-locked loop (D/PLL) architecture for enhanced jitter filtering. All the CDR lanes operate independently while sharing a single voltage-controlled oscillator and supporting referenceless clock acquisition. To reduce power consumption, a multidrop clock distribution scheme with single on-chip transmission-line (T-line) and quadrate RX and TX schemes without CML logic gates are incorporated. Embedded built-in self-test modules featuring a random accumulation jitter generator enables bit error rate (BER) and jitter tolerance self tests without any external equipment. The TX featuring a three-tap pre-emphasis provides a variable output swing ranging from 478 mV $_{\rm ppd}$ to 1.06 V $_{\rm ppd}$ . RX equalizers employing a continuous-time linear equalizer and a one-tap decision feedback equalizer compensate for the channel loss up to 25 dB at the Nyquist rate. The measured RX input sensitivity for a BER of 10 $^{-12}$ is 42 mV $_{\rm ppd}$ . The proposed IC consumes only 0.87 W at 28.0 Gb/s with a BER less than 10 $^{-15}$ on PRBS31 testing. The power efficiency of the proposed transceiver is 3.9 mW/Gb/s, which is the best among the efficiencies achieved by recently published 25 Gb/s transceivers.

Widely linear digital self-interference cancellation in direct-conversion full-duplex transceiver

This paper addresses the modeling and cancellation of self-interference in full-duplex direct-conversion radio transceivers, operating under practical imperfect radio frequency (RF) components. First, detailed self-interference signal modeling is carried out, taking into account the most important RF imperfections, namely, transmitter power amplifier nonlinear distortion as well as transmitter and receiver IQ mixer amplitude and phase imbalances. The analysis shows that after realistic antenna isolation and RF cancellation, the dominant self-interference waveform at the receiver digital baseband can be modeled through a widely linear transformation of the original transmit data, opposed to classical purely linear models. Such widely linear self-interference waveform is physically stemming from the transmitter and receiver IQ imaging and cannot be efficiently suppressed by classical linear digital cancellation. Motivated by this, novel widely linear digital self-interference cancellation processing is then proposed and formulated, combined with efficient parameter estimation methods. Extensive simulation results demonstrate that the proposed widely linear cancellation processing clearly outperforms the existing linear solutions, hence enabling the use of practical low-cost RF front ends utilizing IQ mixing in full-duplex transceivers.

On Rate Region Analysis Of Half- and Full-Duplex OFDM Communication Links

The rate regions of half- and full-duplex links using the orthogonal frequency division multiplexing (OFDM) technique are analyzed after taking into account the non-ideality of practical transceivers. The non-ideality is quantified by a measure named error vector magnitude (EVM) level in practical systems. It is approximated as a Gaussian noise added to the original signal by the transmitter. The assumed full-duplex transceiver suppresses the self-interference via a three-stage process. The stages are antenna isolation, RF cancellation, and digital baseband cancellation. The self-interference caused by the EVM noise and the original signal are suppressed differently in the three-stage process. The optimal power allocation algorithms are developed to maximize the rates of the half- and full-duplex OFDM links under two different strategies. The first one aims at a low complexity design, where each node uniformly allocates the power over sub-carriers, whereas the second one adaptively allocates the power over sub-carriers to achieve the largest rate. Using the developed algorithms, the achieved rate regions under frequency-flat and frequency-selective environments are compared.

Full-Duplex Transceiver System Calculations: Analysis of ADC and Linearity Challenges

Despite the intensive recent research on wireless single-channel full-duplex communications, relatively little is known about the transceiver chain nonidealities of full-duplex devices. In this paper, the effect of nonlinear distortion occurring in the transmitter power amplifier (PA) and the receiver chain is analyzed, alongside with the dynamic range requirements of analog-to-digital converters (ADCs). This is done with detailed system calculations, which combine the properties of the individual electronics components to jointly model the complete transceiver chain, including self-interference cancellation. They also quantify the decrease in the dynamic range for the signal of interest caused by self-interference at the analog-to-digital interface. Using these system calculations, we provide comprehensive numerical results for typical transceiver parameters. The analytical results are also confirmed with full waveform simulations. We observe that the nonlinear distortion produced by the transmitter PA is a significant issue in a full-duplex transceiver and, when using cheaper and less linear components, also the receiver chain nonlinearities become considerable. It is also shown that, with digitally-intensive self-interference cancellation, the quantization noise of the ADCs is another significant problem.

Analysis of Oscillator Phase-Noise Effects on Self-Interference Cancellation in Full-Duplex OFDM Radio Transceivers

This paper addresses the analysis of oscillator phase-noise effects on the self-interference cancellation capability of full-duplex direct-conversion radio transceivers. Closed-form solutions are derived for the power of the residual self-interference stemming from phase noise in two alternative cases of having either independent oscillators or the same oscillator at the transmitter and receiver chains of the full-duplex transceiver. The results show that phase noise has a severe effect on self-interference cancellation in both of the considered cases, and that by using the common oscillator in upconversion and downconversion results in clearly lower residual self-interference levels. The results also show that it is in general vital to use high quality oscillators in full-duplex transceivers, or have some means for phase noise estimation and mitigation in order to suppress its effects. One of the main findings is that in practical scenarios the subcarrier-wise phase-noise spread of the multipath components of the self-interference channel causes most of the residual phase-noise effect when high amounts of self-interference cancellation is desired.

A NEW DESIGN OF DUAL-PORT ACTIVE INTEGRATED ANTENNA FOR 2.4/5.2 GHZ WLAN APPLICATIONS

A new design of dual-port monopole-slot-like microstrip active integrated antenna (AIA) is presented and discussed in this paper. The primary designed passive antenna is capable of supporting two difierent WLAN bands at 2.4{2.84GHz and 5.15{5.35GHz due to its dual-port structure. In order to reduce the transmission coe-cient between the two ports of antenna a coupling sleeve-arm and an inverted T-shaped slot are utilized on the ground plane of antenna each beneath one of the corresponding feed-lines which act as flltering structures at desirable frequencies. The proposed passive dual-port antenna is integrated with a power amplifler (PA) and a low noise amplifler forming a dual- port microstrip AIA which can be used as a full-duplex transceiver at its operating WLAN frequency bands. The measured results for both passive and active antennas show that the designed antennas have proper radiation characteristics at their desired operation frequencies. The fabricated passive antenna exhibits dual-band performance at 2{3.42GHz and 4.5{5.6GHz while the fabricated AIA covers 2.31{ 2.82GHz (at PA port) and 4.45{5.5GHz (at LNA Port) with 13dB and 9dB gain level improvement respectively.

Full-Duplex Crystalless CMOS Transceiver With an On-Chip Antenna for Wireless Communication in a Hybrid Engine Controller Board

A full-duplex transceiver for wireless inter-chip data communication in an engine controller board of hybrid electric vehicles is demonstrated. The amplitude shift keying (ASK) transceiver incorporates a clock data recovery circuit for crystalless operation as well as for simultaneous generation of a 24-GHz local oscillator signal and a 400-MHz clock for data recovery. The transceiver also integrates an on-chip antenna and a duplexer. The bit error rate (BER) degradation of RX due to the full duplex operation of transceiver with an on-chip antenna is negligible when the input power is greater than -44 dBm necessary to achieve a BER of less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> . This is the first demonstration of full duplex operation for an integrated circuit incorporating an on-chip antenna. The transceiver is fabricated in a 130-nm CMOS technology and consumes 245 mW.

Microstrip patch array antenna with high isolation characteristic

The design of an integrated rectangular microstrip patch array antenna with enhanced isolation characteristic between transmitter and receiver is presented to produce a full-duplex transceiver with transmit and receive operation at the same frequency and with the same polarization. This integrated circulator-like antenna has potential uses in both short-range communication systems and radar systems. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:973–976, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26727

DAC Quantization-Noise Cancellation in an Echo-Canceling Transceiver

Data converters, in particular, the transmit digital-to-analog converter (DAC), should not limit performance in a full-duplex digital-communication transceiver. Typically, the number of DAC bits is chosen to be large enough so that the effect of DAC quantization noise on the local receiver is negligibly small. As described in this brief, the DAC quantization noise can be cancelled in an echo-canceling full-duplex transceiver. The proposed quantization-noise cancellation allows use of a simpler, lower resolution DAC. The quantization-noise cancellation concept is described, and simulation results are presented that demonstrate its operation.

60‐GHz transceiver module with coplanar ribbon bonded planar millimeter wave bandpass filter

AbstractA small size 60‐GHz full duplex transceiver module is developed for high data rate millimeter wave wireless access link. To realize a compact and low cost transceiver module, a planar millimeter wave bandpass filter is integrated by using broadband coplanar ribbon‐bond interconnects in the module. The overall size of the module except input and output connectors is 50 mm × 75 mm × 23 mm. The measured RF output power is 16 dBm at 1‐dB compression, with conversion gain of 30.6 dB and the conversion gain of the receiver being 23.4 dB. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 1212–1214, 2007; Published online in Wiley InterScience (www.interscience.wiley.com) DOI 10.1002/mop.22399

A Multiband, Compact, and Full-Duplex Beam Scanning Antenna Transceiver System Operating From 10 to 35 GHz

This paper presents a compact phased-array antenna transceiver system that can operate over a wide bandwidth from 10 to 35 GHz with the abilities of beam scanning and full-duplex communication. The system consists of ultrawide-band Vivaldi antennas, a multiline PET-based phase shifter, a six-channel microstrip multiplexer, and monolithic microwave integrated circuit (MMIC) amplifiers. The multiplexer routes 10, 19, and 32 GHz signals to the transmit path and 12, 21, and 35 GHz signals to the receive path. The multiplexer shows insertion loss between 2.2 and 3.4 dB for all six channels and together with wide-band MMIC amplifiers plays an important role to build a compact, multifrequency, and full-duplex transceiver system. The system should have many applications in multiband satellite communication systems and radar systems.

An 8-Gb/s simultaneous bidirectional link with on-die waveform capture

A full-duplex transceiver capable of 8-Gb/s data rates is implemented in 0.18-/spl mu/m CMOS. This equalized transceiver has been optimized for small area (329 /spl mu/m /spl times/ 395 /spl mu/m) and low power (158 mW) for point-to-point parallel links. Source-synchronous clocking and per-pin skew compensation eliminate coding bandwidth overhead and reduce latency, jitter, and complexity. This link is self-configuring through the use of automatic comparator offset trim and adaptive deskew. Comprehensive diagnostic capabilities have been integrated into the transceiver to provide link, interconnect, and circuit characterization without the use of external test equipment. With a resolution of 4 mV and 9 ps, these capabilities enable on-die eye diagram generation, equivalent time waveform capture, noise characterization, and jitter distribution measurements.

An enhanced joint equalization algorithm for full-duplex DMT transceivers

An objective function incorporating the factors that affect the system throughput is proposed, and an enhanced joint time-domain equalization algorithm is developed for full-duplex discrete multitone (DMT) transceivers. This algorithm is able to shorten the channel and echo impulse responses using a single filter while keeping the system throughput high.

Joint impulse response shortening for DMT transceivers

A new algorithm is proposed for joint impulse response shortening in full-duplex discrete multitone transceivers. In comparison with the previous approach, the proposed algorithm takes into account both the presence of noise and the flexibility of having different signal/noise power distributions.