Full-custom Techniques Research Articles

Maximum Temperature Detection System for Integrated Circuits

Abstract The paper describes structure and measurement results of the system detecting present maximum temperature on the surface of an integrated circuit. The system consists of the set of proportional to absolute temperature sensors, temperature processing path and a digital part designed in VHDL. Analogue parts of the circuit where designed with full-custom technique. The system is a part of temperature-controlled oscillator circuit - a power management system based on dynamic frequency scaling method. The oscillator cooperates with microprocessor dedicated for thermal experiments. The whole system is implemented in UMC CMOS 0.18 μm (1.8 V) technology.

Timepix3: a 65K channel hybrid pixel readout chip with simultaneous ToA/ToT and sparse readout

The Timepix3, hybrid pixel detector (HPD) readout chip, a successor to the Timepix \\cite{timepix2007} chip, can record time-of-arrival (ToA) and time-over-threshold (ToT)simultaneously in each pixel.ToA information is recorded in a 14-bit register at 40 MHz and can be refined by a further 4 bitswith a nominal resolution of 1.5625 ns (640 MHz). ToT is recorded in a 10-bit overflow controlledcounter at 40 MHz. Pixels can be programmed to record 14 bits of integral ToT and 10 bits of eventcounting, both at 40 MHz. The chip is designed in 130 nm CMOS and contains256 × 256 pixel channels (55 × 55 μm2).The chip, which has more than 170 M transistors, has been conceived as a general-purposereadout chip for HPDs used in a wide range of applications. Common requirements of theseapplications are operation without a trigger signal, and sparse readout where only pixels containingevent information are read out.A new architecture has been designed for sparse readout and can achieve a throughput of up to 40 Mhits/s/cm2.The flexible architecture offers readout schemes ranging from serial (one link) readout (40 Mbps) tofaster parallel (up to 8 links) readout of 5.12 Gbps. In the ToA/ToT operation mode, readout is simultaneous withdata acquisition thus keeping pixels sensitive at all times. The pixel matrix is formed by super pixel (SP)structures of 2 × 4 pixels. This optimizes resources by sharing the pixelreadout logic which transports data from SPs to End-of-Column (EoC) using a 2-phase handshakeprotocol.To reduce power consumption in applications with a low duty cycle,an on-chip power pulsing scheme has been implemented. The logic switches bias currentsof the analog front-ends in a sequential manner, and all front-ends can be switched in 800 ns.The digital design uses a mixture of commercial and custom standard cell libraries and was verifiedusing Open Verification Methodology (OVM) and commercial timing analysis tools. The analogfront-end and a voltage-controlled oscillator for 1.5625 ns timing resolution have been designed using fullcustom techniques.

Design and Implementation of a New Real-Time Frequency Sensor Used as Hardware Countermeasure

A new digital countermeasure against attacks related to the clock frequency is –presented. This countermeasure, known as frequency sensor, consists of a local oscillator, a transition detector, a measurement element and an output block. The countermeasure has been designed using a full-custom technique implemented in an Application-Specific Integrated Circuit (ASIC), and the implementation has been verified and characterized with an integrated design using a 0.35 μm standard Complementary Metal Oxide Semiconductor (CMOS) technology (Very Large Scale Implementation—VLSI implementation). The proposed solution is configurable in resolution time and allowed range of period, achieving a minimum resolution time of only 1.91 ns and an initialization time of 5.84 ns. The proposed VLSI implementation shows better results than other solutions, such as digital ones based on semi-custom techniques and analog ones based on band pass filters, all design parameters considered. Finally, a counter has been used to verify the good performance of the countermeasure in avoiding the success of an attack.

Overheat protection circuit for high frequency processors

Overheat protection circuit for high frequency processors The paper describes design and structure of the overheat protection circuit based on the PTAT sensors. The digital core of the system is driven by a 3-bit information generated by the structure. As a result, behaviour of the core differs for each temperature. The circuit was designed in LF CMOS 0.15 μm technology using full-custom technique. The presented paper focuses especially on the structure of the overheat protection circuit and simulations results of the functional blocks of the system. Layout and some parameters of the circuit are also considered.

Full-custom design of Reed-Muller universal logic modules

Abstract Reed-Muller universal logic modules (RM-ULMs) and the development of prototype modules using full-custom techniques are discussed. The design of two-to-one and four-to-one RM-ULMs using 1-5μm CMOS technology is described. Design procedures using CHIPWISE and the SPICE simulation results of the modules are outlined.