Full-chip Optimization Research Articles

Machine Learning Based Variation Modeling and Optimization for 3D ICs

Three-dimensional integrated circuits (3D ICs) experience die-to-die variations in addition to the already challenging within-die variations. This adds an additional design complexity and makes variation estimation and full-chip optimization even more challenging. In this paper, we show that the industry standard on-chip variation (AOCV) tables cannot be applied directly to 3D paths that are spanning multiple dies. We develop a new machine learning-based model and methodology for an accurate variation estimation of logic paths in 3D designs. Our model makes use of key parameters extracted from existing GDSII 3D IC design and sign-off simulation database. Thus, it requires no runtime overhead when compared to AOCV analysis while achieving an average accuracy of 90% in variation evaluation. By using our model in a full-chip variation-aware 3D IC physical design flow, we obtain up to 16% improvement in critical path delay under variations, which is verified with detailed Monte Carlo simulations.

Multi-TSV and E-Field Sharing Aware Full-chip Extraction and Mitigation of TSV-to-Wire Coupling

The through-silicon-via (TSV) introduces new parasitic components into 3-D ICs. This paper presents a novel method of extracting the parasitic capacitance between TSVs and their surrounding wires. For the first time, we examine electrical field (E-field) sharing effects from multiple TSVs and neighboring wires and their impact on timing, power, and noise with full-chip sign-off analyses. For fast and accurate full-chip extraction, we propose a pattern-matching algorithm that accounts for the physical dimensions of multiple TSVs and neighboring wires and captures all E-field interactions. Compared with the average error of a field solver, that of our extraction method, which requires only 2.4 s runtime and negligible memory for a full-chip 64-point fast Fourier transform (FFT64) design with 330 TSVs, is 0.063fF. Upon extraction of TSV-related parasitics, we observe that TSV-to-wire capacitance significantly increase average TSV net noise and the longest path delay. To reduce TSV-to-wire coupling, we implement two full-chip optimization methods and show that increasing the minimum distance between TSVs and neighboring wires reduces both coupling noise and the aggressor count. Thanks to E-field sharing from grounded wire guard rings, victim TSVs are more effectively shielded from aggressor noise. A full-chip analysis shows that these methods are highly effective in reducing noise with only slight impact on timing and area.

SRAF Optimization for sub-40nm Technology Node Contact Patterning

As 193nm immersion lithography is extended to sub-40nm technology node, how to define a single-pass contact hole patterning process with enough common lithography process window is a very challenging task. Sub-resolution assist features (SRAF) optimization is one crucial step besides illumination optimization and mask bias optimization. This paper presents a comprehensive SRAF optimization flow that achieves a set of SRAF solutions that balances SRAF benefits and mask manufacturing feasibility. As the criterion of patterning performance, the through pitch process window is investigated for different SRAF placement options based on simulated PV-band of a given process variation (focus & dose). Full chip optimization with representative layouts is also studied. Silicon level performance verification is done with final SRAF solution for through pitch pattern and typical layouts. Finally, we conclude the paper by demonstrating the overall benefit of SRAF on CD uniformity, from process capability as well as mask complexity perspectives.