Front-end Power Factor Correction Research Articles

Stacked-Switch Power Factor Correction Architecture

Two-stage power factor correction (PFC) architecture, consisting of a boost PFC front end and an isolated DC–DC converter, is widely used in AC–DC applications. However, the boost PFC front end loses zero-voltage-switching (ZVS) at high-line conditions, limiting its practical switching frequency. Consequently, a relatively large boost inductor and EMI filters are needed in the two-stage architecture, leading to a lower power density design. This article proposes a stacked-switch PFC architecture that allows all switches to achieve full-load-range ZVS at a universal input while reducing the component counts compared to the two-stage architecture. As a result, the stacked-switch architecture can operate efficiently at a much higher switching frequency than the two-stage architecture, allowing for higher power density and lower cost. Additionally, this architecture can be operated at a constant switching frequency, which is beneficial for simplifying the magnetics and controller design. A 150-W-universal-input prototype is built to verify the effectiveness of the stacked-switch PFC concept. The prototype measures 92.9 % peak efficiency and 53.9 W/in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^{3}$</tex-math></inline-formula> power density by box volume.

A New PFC Front End With Constant DC-Link Voltage, Reduced Buffer Capacitance, and Soft Switching

Critical conduction mode (CRM) boost power factor correction (PFC) front end is one of the most popular solutions to universal ac–dc applications below 300 W for its simplicity and high efficiency. However, its power density is largely limited by the need for a relatively bulky inductor and a buffer capacitor. This article introduces a new PFC front end that enables simultaneous size reduction of both the inductor and the buffer capacitor by achieving zero-voltage-switching of all switches and active power buffering. A 100-W universal input prototype is built, measuring a 96.7% peak efficiency and 50.8-W/in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^{3}$</tex-math></inline-formula> power density. Compared to a typical CRM boost PFC front end, the prototype achieves a 47% size reduction of the magnetics, a 21% size reduction of the buffer capacitor, and an almost constant dc-link voltage, while maintaining comparable efficiency performance.

Star Power Factor Correction Architecture

Conventional two-stage power factor correction (PFC) architecture based on a boost PFC front end and an isolated dc–dc back end is increasingly challenged by the recent trend toward higher power density and efficiency. One key reason for the challenge is the difficulty of increasing the operating frequency of the boost PFC stage. This article presents a new star PFC architecture that allows the boost PFC stage to operate efficiently at a higher frequency while maintaining the performance of the second dc–dc stage, leading to a high-power-density and high-efficiency ac–dc converter design across a universal input. The high performance of star architecture is enabled by realizing: 1) continuous-conduction-mode (CCM) operation of the boost PFC stage; and 2) full-range zero-voltage-switching (ZVS) of all active switches. In addition, the star architecture can: 1) operate at a constant frequency via a proper selection of the circuit topology and modulation method; and 2) be controlled based on simple and low-cost analog circuits. A 300-kHz, 240-W, 48-V-output, and universal-input prototype is built to verify the performance of the star architecture, showcasing high power factor, constant output voltage, 97.1 % full-load efficiency, 55.6 W/in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^{3}$</tex-math></inline-formula> power density by box volume.

A Review on Two-Stage Back End DC-DC Converters in On-Board Battery Charger for Electric Vehicle

Development in the area of Power Electronics leads to a drastic change in transportation from conventional fuel-based vehicles to Electric vehicles. Due to the adverse effects of conventional transportation to the environment, eco-friendly transportation like e-transportation becomes necessary. In e-transportation battery and its charging system plays a major role. The battery charger can be broadly classified into the on-board charger (OBC) and off-board charger. OBC’s can be further branched into a single stage (AC-DC) converter and two-stage (AC-DC & DC-DC) converter. Due to the limitations of the single-stage converter, two-stage topology becomes more popular. Two-stage topology exists with the front end Power Factor Correction (PFC) stage and back end DC-DC regulating stage. Achieving high power quality and regulation is essential for the battery charger. In this paper, an examination of various topologies of the back end two-stage DC-DC converter with isolated and non-isolated configurations in OBC is done with a brief comparison.

CM Conducted EMI mitigation in flyback PFC converter

The switched mode power supplies offer many advantages in power conversion. But they offer low power factor and generate electromagnetic interference (EMI). The low power factor can be improved by a front-end power factor correction (PFC) unit. However, they also generate EMI in both differential mode and common mode (CM). The interwinding capacitance of the transformer and parasitic capacitance between the heat sink and ground are major contributors to CM noise. The traditional method to minimize the CM noise by using a line filter consists of CM choke and Y capacitor. But, CM noise causes leakage current to flow to the ground through the Y capacitor. This leakage current has to be restricted as per the standards for commercially used equipment and medical instruments. The technique proposed here reduces the values of Y capacitor thereby reducing the leakage current. This can be reduced by minimizing the predominant parasitic capacitances of the HF transformer used in the PFC converter. This paper presents a technique for reducing these parasitic capacitances by incorporating an additional parasitic capacitance noise cancellation winding (PCW). A flyback transformer winding capacitance model depicting the parasitic capacitances is considered, and a novel method to determine this parasitic capacitance is presented. Using this model, the CM Conducted EMI in a flyback PFC is determined by simulation and experimentation. These simulation and experimentation results are used to design an EMI line filter to reduce the Conducted CM noise to complaint levels. The value of Y capacitor now is reduced due to the addition of PCW thereby reducing the size and cost of the filter. This technique has been validated experimentally on a 30-W power factor correction flyback converter working in critical conduction mode.

A High-Power-Density Power Factor Correction Front End Based on Seven-Level Flying Capacitor Multilevel Converter

This paper presents a power factor correction (PFC) front end based on a seven-level flying capacitor multilevel (FCML) boost converter. Compared to the conventional two-level boost converter, the proposed seven-level FCML converter features the use of low-voltage-rated transistors, reduced voltage stress, and high effective switching frequency on the filter inductor. These characteristics of the FCML converter lead to drastic reduction in the filter inductor size while maintaining high efficiency and, therefore, significantly improve the power density of the PFC front end compared to conventional solutions. On the other hand, the small inductance imposes challenges on the PFC control. The dynamics of the seven-level FCML converter has been analyzed, and a feedforward control has been implemented to overcome these challenges. A hardware prototype is designed for universal ac input (90 to 265 Vac), 400-V dc output, and 1.5-kW power rating. Compared to existing solutions, the hardware prototype demonstrates improved efficiency and power density while maintaining high power factor and low THD. A power density of 219 W/in3 (490 W/in3 for the power stage) has been achieved, and a peak efficiency of 99.07% has been experimentally verified.

Control of Direct Voltage Regulated Active DC-Link Capacitance Reduction Circuits to Allow Plug-and-Play Operation

A novel method for controlling direct voltage regulated active dc-link capacitance reduction circuits (ACRC) is proposed in this paper. Instead of forcing the dc-link voltage of the power conversion system to follow a constant reference, the ACRC imposes dc-bus voltage in proportion to the integral of its input current. Consequently, it resembles an adjustable value capacitor from the dc-link side. Therefore, as opposed to existing control strategies, the proposed method simultaneously allows the dc-link voltage to reflect the power balance of the system and the pulsating power component to be diverted into significantly reduced auxiliary capacitance via a bidirectional dc-dc converter. As a result, replacing bulk dc-link capacitance by the proposed circuitry does not require any modification of existing grid-connected power conversion system controllers, thus allowing plug-and-play operation. The proposed approach is validated by application to a commercial power factor correction front end by both simulations and experiments.

Simple and straightforward realisation of an electronic capacitor

This Letter proposes a simple realisation of a circuit (referred to as electronic capacitor) capable of emulating large capacitance of controllable value while utilising a much smaller capacitor and a DC–DC converter. The circuit may be used in a plug-and-play fashion instead of any real large capacitor within the control bandwidth. The proposed control algorithm forces the terminal voltage of the DC–DC converter to follow the well-known capacitance equation by sensing the terminal current and simultaneously compensates conversion losses by an auxiliary control loop. The proposed algorithm is successfully verified by emulating bulk DC-link capacitance of a commercial power factor correction front end.

Modified Dual Output Cuk Converter-Fed Switched Reluctance Motor Drive With Power Factor Correction

The control of a switched reluctance motor (SRM) drive is proposed with a front end power factor correction (PFC) converter. It uses a modified Cuk converter-fed SRM drive to improve power quality at ac mains. The converter configuration consists of two Cuk converters and each of them operates separately for two half-cycles of the supply voltage. The proposed converter generates two identical voltages across two output capacitors to feed a split capacitor converter of a four-phase SRM drive. The proposed pulsewidth modulated ac–dc converter operates in the discontinuous conduction mode to reduce its size and cost by eliminating couple of sensor requirements. The incorporated voltage control loop regulates the dc-link voltage with PFC at ac mains. The SRM is considered for the proposed drive because of its low cost and constructional ease. The motor speed is controlled over a wide range by regulating the PFC converter output dc voltage. The proposed SRM drive is tested for steady-state and dynamic state conditions on a developed prototype in the laboratory. The obtained test results demonstrate good drive performance and line drawn power quality. The input current total harmonic distortion is observed within a limit of a standard.

Comparative Evaluation of Front- and Back-End PFC IPT Systems for a Contactless Battery Charger

Inductive power transfer (IPT) is widely discussed as an alternative to contact charger for plug-in hybrid and electric vehicles. This paper analyzes a contactless battery charger back-end power factor correction (PFC) concept, reducing the primary-side circuit complexity and physical size. For that purpose, the main volume and loss factors of a contactless battery charger are identified, discussing the partitioning of tasks to perform a unity power factor operation. An analysis of the most commonly used front-end PFC and the proposed back-end PFC configuration is performed, with the aim of highlighting benefits and limitations of each variant. Moreover, performance of silicon (Si) and gallium nitride (GaN) devices has also been evaluated, defining the main advantages and drawbacks of both semiconductor technologies in different IPT scenarios. The study is verified experimentally on a 3.2 kW contactless battery charger.

A Compact Electrolytic-Free Two-Stage Universal Input Offline LED Driver With Volume-Optimized SSC Energy Buffer

This paper presents a single-phase, two-stage electrolytic-free offline LED driver that utilizes a hybrid film-ceramic stacked switched capacitor (SSC) energy buffer in place of limited-life electrolytic capacitors for twice-line-frequency energy buffering. The proposed LED driver comprises a front-end power factor correction (PFC) stage, followed by an isolated dc–dc conversion stage, with an SSC energy buffer connected across the intermediate dc bus. For the design of SSC energy buffer, an improved capacitance ratio optimization methodology is presented that incorporates the energy densities of commercially available capacitors and minimizes the passive volume of the buffer. Compared to a single capacitor, the optimized SSC energy buffer, comprising three switches, reduces the passive volume of the energy buffer by greater than 40%. A simple and robust control scheme is also proposed to interface the SSC energy buffer with the PFC converter. A prototype 300-W LED driver based on the proposed architecture, designed for universal input voltage range (90–305 Vrms) and 12-V output voltage is built and tested. The SSC energy buffer achieves a peak efficiency of 98.5% and maintains an efficiency of above 96% across a wide output power range, thus minimally impacting the overall system efficiency. Finally, the impact of the intermediate dc-bus voltage ripple on overall LED driver efficiency is investigated. It is found that there is negligible change in the efficiency when the intermediate dc-bus voltage ripple ratio is varied between 3% and 7.5%.

Design and Implementation of Sensorless Voltage Control of Front-End Rectifier for Power Quality Improvement in Telecom System

In this paper, a three-phase three-switch three-level boost (Vienna) type pulse-width modulation rectifier is proposed as an active front-end power factor correction (PFC) rectifier for power quality improvement in telecom load. A sensorless voltage control technique is proposed and it does not rely on any input voltage information results in reliable and robust operation. A brief description on the principle of operation and the most advantageous modulation method of the proposed system are discussed. The feasible switching states are identified for the proposed active front-end converter resulting in reduced switching stress and dc ripples. A triangular carrier based control logic is applied and the input current reaches sinusoidal shape without the need of sensing the input voltage. The detailed analysis of front-end PFC converter is carried out by equivalent circuit analysis. Also, the complete loss and efficiency calculation of the converter is explicitly carried out with the help of hardware design guidelines. The performance of the proposed system and its capability of operating satisfactorily in the event of failure of one phase of the mains is verified through MATLAB Simulation, and the results obtained are presented. The experimental setup rated for 9 kW is developed in the laboratory to validate the simulation results. From the simulation and hardware results, it is observed and recorded that the power quality parameters are improved and are well within the IEEE and IEC standards.

A High Step-Down Isolated Three-Phase AC-DC Converter

In this paper, a single-stage three-phase isolated ac-dc converter topology utilizing SiC MOSFETs is proposed for power rectification with a stepped-down output voltage. Unlike the conventional two-stage [front-end power factor correction (PFC) stage and isolated dc-dc stage] ac-dc converters, the full/half bridge structure in dc-dc stage is eliminated in this structure. The high-frequency pulsating voltage is obtained directly from the PFC stage and is applied across the high-frequency transformer, leading to a more compact design. In addition, there is an advantage of zero voltage switching (ZVS) in four PFC MOSFETs connected to the high-frequency tank, which is not achievable in the case of a conventional two-staged ac-dc converter. A sine-pulse width modulation (PWM)-based control scheme is applied with the common-mode duty ratio injection method to minimize the current harmonics without affecting the power factor. An LC filter is used after the PFC semistage to suppress the line-frequency voltage ripple. Furthermore, the intermediate dc-link capacitor value can be greatly reduced through no additional ripple constraints. Experimental and simulation results are included for a laboratory prototype, which converts 115-V, 400-Hz three-phase input voltage to 28-V dc output voltage. The experimental results demonstrate a power factor of 0.993 with a conversion efficiency of 95.4%, and total harmonic distortion (THD) as low as 3.5% at 2.1-kW load condition.

BLDC Motor Drive Based on Bridgeless Landsman PFC Converter With Single Sensor and Reduced Stress on Power Devices

The Landsman converter based on a power factor correction (PFC) in bridgeless (BL) configuration feeding a brushless dc motor (BLDCM) drive is proposed for low-power household appliances. The conduction losses associated with diodes are reduced by BL configuration and switching losses of solid-state switches of voltage source inverter are reduced by the use of low frequency switching signals in electronic commutation for the BLDCM. The front-end BL PFC based Landsman converter operating in the discontinuous inductor current mode is used for controlling the dc link voltage, and PFC is attained naturally with reduced conduction losses and switch stress. A single voltage sensor is used for controlling the dc bus voltage. A prototype is developed to study performance of the system for wide range speed control and power quality improvement. The experimental performance of BLDCM is presented for its functions at varying voltages of ac mains (90–265 V) to adhere to the limits defined by IEC61000-3-2 standard.

Implementation of a 3.3-kW DC–DC Converter for EV On-Board Charger Employing the Series-Resonant Converter With Reduced-Frequency-Range Control

A control method that improves performance of series-resonant converters that operate with a wide input voltage and/or output voltage range by substantially reducing their switching frequency range is introduced. The switching-frequency-range reduction is achieved by controlling the output voltage with a combination of variable-frequency and delay-time control. Variable-frequency control is employed to control the primary switches, while delay-time control is used to control secondary-side rectifier switches provided in place of diode rectifiers. A series-resonant converter with the proposed control method is employed as the output stage of the on-board charger module that operates with a wide battery-voltage range. By substantially reducing the switching frequency range, the overall operating frequency is increased to reduce the sizes of the passive components, and hence, increase power density. The performance evaluation of the proposed series-resonant converter with delay-time control was done on a 3.3-kW prototype delivering energy from 400-V bus, which is the output of the power factor correction front end, to a battery operating with voltage range between 180 and 430 V. Two implementations of the prototype circuit, one employing gallium nitride (GaN) and the other employing silicon (Si) switches, were evaluated and compared. The prototype with Si switches that at full load over the entire output voltage range operates with a switching frequency variation from approximately 150 to 190 kHz exhibits the maximum full-load efficiency of 98.1%, whereas the corresponding frequency range and efficiency of the prototype with GaN devices are 145–190 kHz and 97.4%, respectively.

A Novel ZVS DC–DC Full-Bridge Converter With Hold-Up Time Operation

Two stage ac–dc converters consisting of front-end power factor correction ac–dc boost converter followed by an isolated dc–dc converter form the industry workhorses for powering network servers, telecom, and other dc loads. For safe and uninterrupted operation during sudden intermittences in power supplied from the ac mains, the ac–dc power converter should be able to supply the load with constant dc output voltage in order to prevent them from unwanted resetting or in other words exhibit sufficient hold-up time (HUT) operation. This paper proposes a novel dc–dc nonresonant full-bridge converter with extended HUT capability and reduced dc-link storage capacitance.

Low-Frequency DC-Link Ripple Elimination in Power Converters With Reduced Capacitance by Multiresonant Direct Voltage Regulation

In this paper, a method for suppressing the low-frequency portion of dc-link ripple inevitably present in power conversion systems with reduced capacitance is proposed. The discussed active capacitance reduction circuitry (consisting of a feedback-controlled shunt-connected bidirectional buck-boost converter, terminated by a small auxiliary capacitance) directly regulates the dc-link voltage, utilizing a dual-loop control structure with parallel-connected multiresonant-bank-enhanced voltage loop stabilizing controller to achieve nearly constant, low-frequency-ripple-free steady-state dc-link voltage. Consequently, the proposed active capacitance reduction system may be perceived as a virtual infinite capacitor from the dc link point of view. The suggested circuitry is successfully applied to a single-phase commercial power factor correction front end in a nearly plug-and-play fashion. The control algorithm effectiveness is fully supported by simulations and experimental results.

A Polynomial Current Controller for a Third-Harmonic Modulated Power Factor Correction Rectifier Feeding a Vector Controlled Induction Motor Drive

This paper presents the analysis, design, and hardware implementation of a digital polynomial Regulation, Steady-State Error and Tracking (RST) current controller-based third-harmonic modulated boost-type power factor correction (PFC) rectifier. The proposed rectifier is used at the front end of a vector controlled induction motor drive (VCIMD) to eliminate harmonics at the input AC supply. The proposed PFC rectifier modifies the input current to a sinusoid with unity power factor apart from offering DC bus voltage regulation. In this paper, a digital proportional-integral (PI) and RST current controllers are compared in terms of total harmonic distortion (THD) and power factor (PF) at the point of common coupling for different loading conditions. The RST current controller tracks the set-point accurately with zero steady-state error and offers good disturbance rejection that enables further reduction of supply current THD as compared to a conventional PI current controller. The control algorithm for the PFC front end rectifier along with vector control technique is implemented using a digital signal processor, and the dynamic performance is analyzed for step changes in reference speed and load torques, demonstrating significant improvement in the performance indices.

A Multimode 1-MHz PFC Front End With Digital Peak Current Modulation

This work presents a novel mixed-signal control scheme for a boost power factor correction (PFC) rectifier. The digital controller modulates the inductor peak current to produce a low-distortion ac line current in discontinuous conduction mode (DCM) and continuous conduction mode (CCM), without the need for average current sensing. A lookup table (LUT) optimizes efficiency at low input currents, by allowing operation at 125–500-kHz DCM based on calculated thresholds. At high input currents, the converter operates at 1-MHz CCM for reduced inductor footprint. An analog off-time generator with a digital frequency locked loop facilitates CCM operation, eliminating the need for slope compensation in the current loop and reduces frequency variations. The LUT is programmed with an adaptive output voltage of 250/450 V for low/high mains line voltage (85–265 Vrms) to optimize efficiency over a broad range of conditions. The 150-W PFC prototype operates up to 1 MHz with a peak efficiency of 95% and a total harmonic distortion of 5%.

Development of a Novel 30 kV Solid-state Switch for Damped Oscillating Voltage Testing System

This paper describes the design and development of a novel semiconductor-based solid-state switch for damped oscillating voltage test system. The proposed switch is configured as two identical series-connected switch stacks, each of which comprising 10 series-connected IGBT function units. Each unit consists of one IGBT, a gate driver, and an auxiliary voltage sharing circuit. A single switch stack can block 20 kV-rated high voltage, and two stacks in series are proven applicable to 30 kV-rated high voltage. The turn-on speed of the switch is approximately 250 ns. A flyback topology-based power supply system with a front-end power factor correction is built for the drive circuit by loosely inductively coupling each unit with a ferrite core to the primary side of a power generator to obtain the advantages of galvanic isolation and compact size. After the simulation, measurement, and estimation of the parasitic effect on the gate driver, a prototype is assembled and tested under different operating regimes. Experimental results are presented to demonstrate the performance of the developed prototype.