Front-end Part Research Articles

An X-ray detector using PIN photodiodes for the axion helioscope

An X-ray detector for a solar axion search was developed. The detector is operated in a cryostat of a superconducting magnet. Special care was paid to microphonic noise tolerance and mechanical tightness against thermal contraction. The detector consists of an array of 16 PIN photodiodes and tailor made preamplifiers. The size of each PIN photodiode is 11×11×0.5 mm 3 . The detector consists of two parts, the front-end part being operated at a temperature of 60 K and the main part at room temperature. Under these circumstances, the detector achieved an energy resolution of 1.0 keV in FWHM, a threshold of 2.5 keV and a background level of 6×10 −5 counts s −1 keV −1 cm −2 .

Early load address resolution via register tracking

Higher microprocessor frequencies accentuate the performance cost of memory accesses. This is especially noticeable in the Intel's IA32 architecture where lack of registers results in increased number of memory accesses. This paper presents novel, non-speculative technique that partially hides the increasing load-to-use latency, by allowing the early issue of load instructions. Early load address resolution relies on register tracking to safely compute the addresses of memory references in the front-end part of the processor pipeline. Register tracking enables decode-time computation of register values by tracking simple operations of the form reg±immediate. Register tracking may be performed in any pipeline stage following instruction decode and prior to execution. Several tracking schemes are proposed in this paper: Stack pointer tracking allows safe early resolution of stack references by keeping track of the value of the ESP register (the stack pointer). About 25% of all loads are stack loads and 95% of these loads may be resolved in the front-end. Absolute address tracking allows the early resolution of constant-address loads. Displacement-based tracking tackles all loads with addresses of the form reg±immediate by tracking the values of all general-purpose registers. This class corresponds to 82% of all loads, and about 65% of these loads can be safely resolved in the front-end pipeline. The paper describes the tracking schemes, analyzes their performance potential in a deeply pipelined processor and discusses the integration of tracking with memory disambiguation.

Six-Port Receiver and Frequency Measurement for Radar Applications at 35GHz

The application of a six-port technology in the receiving part of a radar front-end is described in this paper. This receiver allows measuring magnitude and phase of the radar signal without the need of down-conversion. According to the applications and the availability of the devices needed for assembling the prototype sensor, the frequency of operation was set to 35GHz. The structure of this six-port as well as the calibration and measurement algorithms are described in detail. The accuracy of the phase measurement is 2–10° depending on the power level of the signal. Another key element of the proposed radar sensor is a direct frequency counter. Using this circuit it is possible to measure the frequency of operation with a resolution of 20 bits within 120μs. The accuracy of the distance reading of the radar is directly related to the accuracy of the frequency measurement and has reached 0.1mm.

System Design of a Proton Linac for the Neutron Science Project at Japan Atomic Energy Research Institute

The Japan Atomic Energy Research Institute has been proposing the Neutron Science Project (NSP). The NSP requires pulse and CW proton beams with an energy of 1.5 GeV and an average beam power up to 8 MW. This paper describes design concepts and parameters of the linac. A front end part of the linac, which consists of RFQ, DTL and SDTL sections, uses normal conducting structures and a high energy part uses superconducting (SC) structures. The linac has two injector lines for the pulse and the CW modes, respectively, and the two lines merge at 7 MeV. The total linac length is approximately 900 m and most of the part (>75%) is the superconducting section. An equipartitioning design, which is a new idea to suppress an emittance growth for high power linacs, has been taken for the DTL, the SDTL and the SC sections. Compared with the conventional constant phase advance design scheme, the equipartitioning design scheme is proved to be a good approach to suppress the longitudinal emittance growth.

System Design of a Proton Linac for the Neutron Science Project at Japan Atomic Energy Research Institut.

The Japan Atomic Energy Research Institute has been proposing the Neutron Science Project (NSP). The NSP requires pulse and CW proton beams with an energy of 1.5 GeV and an average beam power up to 8 MW. This paper describes design concepts and parameters of the linac. A front end part of the linac, which consists of RFQ, DTL and SDTL sections, uses normal conducting structures and a high energy part uses superconducting (SC) structures. The linac has two injector lines for the pulse and the CW modes, respectively, and the two lines merge at 7 MeV. The total linac length is approximately 900 m and most of the part (>75%) is the superconducting section. An equipartitioning design, which is a new idea to suppress an emittance growth for high power linacs, has been taken for the DTL, the SDTL and the SC sections. Compared with the conventional constant phase advance design scheme, the equipartitioning design scheme is proved to be a good approach to suppress the longitudinal emittance growth.

0.5-μm CMOS circuits for demodulation and decoding of an OFDM-based digital TV signal conforming to the European DVB-T standard

In the context of digital terrestrial TV based on the DVB-T standard, four 0.5-/spl mu/m CMOS IC's (IC1-IC4) are presented. IC1 integrates an 8-K fast Fourier transform for orthogonal frequency division multiplexing demodulation, IC2 performs channel estimation/correction, and IC3 is a forward error corrector implementing a Viterbi and a Reed-Solomon decoder. IC4, which is based on a digital signal-processing core, performs the synchronization tasks of the complete receiver. These four chips have been designed and manufactured using a 0.5-/spl mu/m, 3,3-V, triple-metal CMOS process. Their global complexity is about 500 kgates of standard cells and 1.5 Mbits of memory, which represents a total die area of 435 mm/sup 2/ in 0.5 /spl mu/m. The total power dissipation is about 3.5 W when working at nominal frequency. More generally, these four IC's constitute the digital front-end part of a global chipset receiver (specified within the European project DVBird), also including an analog front end and a MPEG2 demultiplexer IC.

A multi-parameter system for acquisition, monitoring, and analysis of scanning ion microprobe data

The multi-parameter data-acquisition system for the Eindhoven scanning ion microprobe set-up is described. The front-end part of the system is based on an M68030 in VME and handles real-time data acquisition, experiment control and data transport. It is linked to a DEC ALPHA-AXP workstation for data storage, on-line data monitoring and data analysis and off-line data analysis. The system can be used to apply simultaneously the micro-PIXE, NBS and NFS techniques to determine elemental concentration distributions on biomedical samples, but can also be used for coincident ion scattering experiments and time or dose dependent studies of e.g. ion-beam induced radiation damage.

Improvement ideas for heavy-ion fusion linacs

In the first part of this article the question of frequency choice of the front-end part of a HIF linac is revisited. Scaling of the plasma frequency o