Front-end Electronics Chain Research Articles

New electronics for the HADES MDC drift chambers

The drift chambers of the HADES experiment at SIS-18 at GSI, Darmstadt/Germany, form the main tracking system of the spectrometer. Designed more than twenty years ago, the whole front-end electronics chain is being replaced with state-of-the-art electronics to cope with the increasing failure rate of the old electronics and with advanced requirements of the experiment, e.g. the trigger rate.The new analog signal processing is based on the PASTTREC ASIC, developed for the Straw Tube Tracker of the PANDA Experiment. The digitization of data happens in FPGA-based TDCs.The main challenges of the project are the strict spatial constraints given by the experiment setup to place the front-end boards and the noise sensitivity of the large area gas detectors. In addition, the power consumption needed to be kept low due to thermal constraints.

Design of a Time-to-Digital Converter ASIC and a mini-DAQ system for the Phase-2 upgrade of the ATLAS Monitored Drift Tube detector

We present the second prototype of a time-to-digital (TDC) ASIC for the upgrade of the ATLAS Monitored Drift Tube (MDT) detector for High-Luminosity LHC operations. Compared to the first prototype, triple modular redundancy has been implemented for the configuration and flow control logic. The total power consumption is increased by less than 10 mW while achieving the same time resolution and channel uniformity. A mini-DAQ system has been built to verify the front-end electronics chain with the new prototype together with other ASICs and boards in triggered mode. Cosmic ray tests with a small-diameter MDT chamber indicate that the configuration and data transmission of the readout electronics perform well. It is expected that this prototype design will be used in the final production.

A Sub-Sampling Approach for Data Acquisition in Gamma Ray Emission Tomography

State of the art data acquisition systems for small animal imaging gamma ray detectors often rely on free running Analog to Digital Converters (ADCs) and high density Field Programmable Gate Arrays (FPGA) devices for digital signal processing. In this work, a sub-sampling acquisition approach, which exploits a priori information regarding the shape of the obtained detector pulses is proposed. Output pulses shape depends on the response of the scintillation crystal, photodetector’s properties and amplifier/shaper operation. Using these known characteristics of the detector pulses prior to digitization, one can model the voltage pulse derived from the shaper (a low-pass filter, last in the front-end electronics chain), in order to reduce the desirable sampling rate of ADCs. Fitting with a small number of measurements, pulse shape estimation is then feasible. In particular, the proposed sub-sampling acquisition approach relies on a bi-exponential modeling of the pulse shape. We show that the properties of the pulse that are relevant for Single Photon Emission Computed Tomography (SPECT) event detection (i.e., position and energy) can be calculated by collecting just a small fraction of the number of samples usually collected in data acquisition systems used so far. Compared to the standard digitization process, the proposed sub-sampling approach allows the use of free running ADCs with sampling rate reduced by a factor of 5. Two small detectors consisting of Cerium doped Gadolinium Aluminum Gallium Garnet (Gd3Al2Ga3O12 : Ce or GAGG:Ce) pixelated arrays (array elements: $2\times 2\times 5~\mathrm {mm}^{3}$ and $1\times 1\times 10~\mathrm {mm}^{3}$ respectively) coupled to a Position Sensitive Photomultiplier Tube (PSPMT) were used for experimental evaluation. The two detectors were used to obtain raw images and energy histograms under 140 keV and 661.7 keV irradiation respectively. The sub-sampling acquisition technique (10 MHz sampling rate) was compared with a standard acquisition method (52 MHz sampling rate), in terms of energy resolution and image signal to noise ratio for both gamma ray energies. The Levenberg-Marquardt (LM) non-linear least-squares algorithm was used, in post processing, in order to fit the acquired data with the proposed model. The results showed that analog pulses prior to digitization are being estimated with high accuracy after fitting with the bi-exponential model.

A 256 channel 8-Bit current digitizer ASIC for the Belle-II PXD

The international DEPFET collaboration is developing a silicon pixel vertex detector (PXD), based on monolithic arrays of DEPFET transistors, for the future physics experiment Belle-II at the SuperKEKB particle accelerator in Japan. The matrix elements are read out in a 'rolling shutter mode', i.e. rows are selected consecutively and all columns are read out in each cycle of < 100 ns.One of the major parts in the front-end electronics chain is the DEPFET Current Digitizer ASIC (DCDB). It is now in a close-to-final state. The chip provides 256 channels of analog-to-digital converters with a resolution of six to eight bits. Each converter features an individual dynamic offset correction circuit as well as programmable gain and bandwidth. Several operation modes using single sampling or double correlated sampling are possible.A large synthesized digital block is used for decoding and derandomization of the conversion results. The data is put out on eight 8-bit links, operating at a speed of 400 MHz. Additionally, a JTAG compatible interface is implemented for configuration and debugging purpose.Significant effort was made to reduce the power consumption of the DCDB, since both, voltage drop on the internal power buses and heat sources in the Belle-II experiment are a concern.The chip was realized on a 3.2mm × 5mm die using the UMC 180nm CMOS technology in a multi-project wafer run, provided by EuroPractice. An extra redistribution metal layer with bump bond pads is used, allowing for flipping the chip onto the final all-silicon DEPFET sensor module.Several tests have been performed in order to prove the chip's operation and its quality in terms of noise. The results are presented.

A new front-end electronics chain for timing RPCs

Recent advances in electronics and counter construction techniques have pushed the timing resolution of resistive plate chambers below 50 ps /spl sigma/, with a detection efficiency of 99% for minimum ionizing particles. In this paper, we describe a new front-end electronic chain for accurate time and charge measurement in these devices. The circuit includes a fast (2.5 GHz) two-stage amplifier based on monolithic microwave integrated circuits that feeds a fixed threshold discriminator followed by an external time-to-digital converter. The amplified signal is also buffered into an external charge-to-digital converter. All components are commercially available and their number is rather reduced. The system was tested with realistic detector-generated test signals, yielding a timing resolution around 10 ps /spl sigma/ for signal charges above 100 fC and a charge resolution of 3.2 fC.

Radiation hard electronics for LHC

A CMOS front end electronics chain is being developed by the RD20 collaboration for microstrip detector readout at LHC. It is based on a preamplifier and CR-RC filter, analogue pipeline and an analogue signal processor. Amplifiers and transistor test structures have been constructed and evaluated in detail using a Harris 1.2 μm radiation hardened CMOS process. Progress with larger scale elements, including 32 channel front end chips, is described. A radiation hard 128 channel chip, with a 40 MHz analogue multiplexer, is to be submitted for fabrication in July 1994 which will form the basis of the readout of the tracking system of the CMS experiment.

Front end electronics for silicon tracking at LHC

A CMOS front end electronics chain is being developed by the RD20 collaboration in a CERN R&D programme for silicon microstrip readout at LHC. It is based on a preamplifier and CR-RC filter, analogue pipeline and an analogue signal processor which implements a deconvolution algorithm. The system is described and latest results on performance presented, including the status of implementation in radiation hard technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>