In this paper, it has been shown that employing an underlap channel created by using the dual spacers in dopant-segregated Schottky barrier (DSSB) SOI MOSFET not only reduces the off-state leakage, short-channel effects and the parasitic overlap capacitances but also suppresses the variability induced by process fluctuations in the Schottky barrier height, dopant-segregation length and SOI film thickness of the device. However, the reduced effective gate voltage due to voltage drop across the underlap lengths also reduces the on-state drive current of the device. To alleviate this trade-off, a novel dual-k spacer underlap channel DSSB SOI structure has also been proposed in which the increased fringing electric field effect due to high-k inner spacer layer not only improves the on-state drive current but also reduces the off-state leakage current in both n-channel and p-channel devices. Despite the presence of high-k inner spacer layer increasing the fringing gate capacitance, the scalability in an optimized dual-k spacer underlap structure has improved by ∼60% and ∼35%, respectively over the conventional spacer overlap and underlap channel structures. In addition, the variability in an optimized dual-k spacer underlap structure has also been reduced by ∼50% and ∼30% respectively over the conventional spacer overlap and underlap channel structures. This clearly indicates that the proposed dual-k spacer underlap structure is a better choice for low-variability nanoscale CMOS logic circuits. The detailed fabrication flow of this novel device has also been proposed which demonstrates the use of conventional CMOS processes.