Frequency Divider Circuit Research Articles

Near-Field Probing of Microwave Oscillators with Josephson Microscopy.

Voltage-controlled oscillators, serving as fundamental components in semiconductor chips, find extensive applications in diverse modules such as phase-locked loops, clock generators, and frequency synthesizers within high-frequency integrated circuits. This study marks the first implementation of superconducting Josephson probe microscopy for near-field microwave detection on multiple voltage-controlled oscillators. Focusing on spectrum tracking, various phenomena, such as stray spectra and frequency drifts, were found under nonsteady operating states. Parasitic electromagnetic fields, originating from power supply lines and frequency divider circuits, were identified as sources of interference between units. The investigation further determined optimal working states by analyzing features of the microwave distributions. Our research not only provides insights into the optimization of circuit design and performance enhancement in oscillators but also emphasizes the significance of nondestructive near-field microwave microscopy as a pivotal tool in characterizing integrated millimeter-wave chips.

The Study on Single-Event Effects and Hardening Analysis of Frequency Divider Circuits Based on InP HBT Process.

The single-event effects (SEEs) of frequency divider circuits and the radiation tolerance of the hardened circuit are studied in this paper. Based on the experimental results of SEEs in InP HBTs, a transient current model for sensitive transistors is established, taking into account the influence of factors such as laser energy, base-collector junction voltage, and radiation position. Moreover, the SEEs of the (2:1) static frequency divider circuit with the InP DHBT process are simulated under different laser energies by adding the transient current model at sensitive nodes. The effect of the time relationship between the pulsed laser and clock signal are discussed. Changes in differential output voltage and the degradation mechanism of unhardened circuits are analyzed, which are mainly attributed to the cross-coupling effect between the transistors in the differential pair. Furthermore, the inverted output is directly connected to the input, leading to a feedback loop and causing significant logic upsets. Finally, an effective hardened method is proposed to provide redundancy and mitigate the impacts of SEEs on the divider. The simulation results demonstrate a notable improvement in the radiation tolerance of the divider.

Design of Frequency Divider (FD/2 and FD 2/3) Circuits for a Phase Locked Loop

This paper reports on three design of Frequency Divider (FD/2) and Frequency Divider (FD 2/3) circuits. Tanner EDA tool developed on 130nm CMOS technology with a voltage supply of 1.3 V is used to build, model, and compare all circuits. For the FD/2 circuit, E-TSPC Pass Transistor logic uses 1.77 µW, whereas TSPC logic consumes 5.57 µW for the FD 2/3 circuit. It implies that the TSPC logic is the best solution since it meets the speed and power consumption requirements.

A Low Power, Low Phase Noise, 11.8 GHz LC-VCO in 65 nm CMOS for 5G NR Based C-V2X Applications

An 11.8-GHz low-power, low phase noise, 65-nm CMOS LC-VCO for V2X communication standards is presented in this work. To achieve low-phase noise performance to fulfill the 5G NR C-V2X standards, several adjustments are made to the conventional LC-VCO topologies. These adjustments are briefly explained in this work. Presented VCO consumes 3.046[Formula: see text]mA current from a 1.2-V power supply. It has [Formula: see text]116.13[Formula: see text]dBc/Hz phase noise at 1[Formula: see text]MHz offset and tuning range between 11.64[Formula: see text]GHz and 11.94[Formula: see text]GHz. A frequency divider circuit is designed and implemented to the presented VCO to satisfy the frequency spectrum of V2X radio access technologies. To the best of authors’ knowledge, this work is the first VCO implemented at 11.8 GHz in a 65-nm CMOS process with the reported phase noise number for 5G NR C-V2X applications.

Design and simulation of frequency divider circuit based on multisim

Frequency divider circuit is the basic circuit in digital logic circuit. The circuit function is to divide or drop the frequency of the high frequency signal to get the lower frequency signal for a given frequency signal by division. On the Multisim software platform, using different design methods, as the foundation of middle scale integration chip 74LS161, design even frequency divider, odd frequency divider circuit and (N- 0.5) frequency divider circuit respectively. Each circuit design principle and method is illustrated and simulated. The results showed that the design is correct and conform to the proposed requirement. Experimental teaching applications based on Multisim software can improve design efficiency and reduce development time of design systems.

Analogue feed‐forward carrier recovery for millimetre‐wave broadband wireless links

An analogue modulation-type independent feed-forward carrier recovery approach for broadband wireless communication systems is introduced in this work. The focus is on the deliberately increased local oscillator (LO) signal feed-through to the radio frequency (RF) port of the up-converter in a direct conversion transmitter (TX). The strong LO feed-through is used at the receiver (RX) side to demodulate the RF signal. The heart of the carrier recovery block is a narrowband bandpass filter (BPF) and a frequency divider-by-n operated in injection-locking mode to the strong LO feed-through. The proposed method is investigated through circuit level simulations; while its feasibility is examined via the successful demodulation of complex data with various modulation types up to 8 Gbps for an E-band front-end. This method can be used for transceivers working at high carrier frequencies as far as the realisation of frequency divider circuits and narrowband BPFs is technically feasible.

Design and Optimization of Dual-Band Energy-Efficient OOK UWB Transmitter Via PSO Algorithm

A CMOS ON–OFF-keying 3–10.6-GHz transmitter with low power consumption and low complexity used to Impulse Radio Ultra-Wide Band (IR-UWB) communication system is presented in this work. This architecture is designed and optimized via particle swarm optimization (PSO) algorithm. The IR-UWB transmitter is adapted to generate a high bandwidth frequency and it has a band switching capability. It consists of a switching inductance–capacitance voltage-controlled oscillator (LC_VCO), a pulse generator circuit, an injection-locked frequency divider (ILFD) circuit, a buffer and an antenna. The VCO is switched ON/OFF by the pulse signal produced by a generator circuit which is realized through synchronizing the received data by a clock signal. The used technique for transmitting a discontinuous signal is based on a complementary switch-mode ON–OFF LC_VCO, whose main advantage is to reduce power consumption. In this work, a best agreement between the results of the optimization technique and those of the simulation is obtained. The simulated results illustrate a signal of pulse width of 2.5 ns and a pulse repetition rate (PRR) of 200 MHz. The output spectra are centered at 4-GHz and 8-GHz frequencies with 1,332-MHz and 1,350-MHz bandwidths, respectively. The peak-to-peak amplitude of a UWB signal output is 154[Formula: see text]mV. The IR-UWB transmitter power consumption is 11.4[Formula: see text]mW which corresponds to the consumption energy of 28.5 pJ/pulse @ 200[Formula: see text]MHz. The power spectral densities (PSDs) of the output signals of both circuits viz. ON–OFF LC_VCO and ILFD are less than [Formula: see text][Formula: see text]dBm/MHz, which agreed well with the Federal Communication Commission (FCC) regulation. The transmitter design is well implemented using a TSMC 0.18-[Formula: see text]m CMOS process technology in an Advanced Design System (ADS).

Design of Low Power, Low Jitter PLL for WiMAX Application in 0.18µm CMOS Process

A low power, low jitter high performance Phase Locked Loop (PLL) based on closed loop Phase Frequency Detector (PFD) and novel Gain-Boosting Charge Pump (GB-CP) technique are shown in this study. The proposed work for WiMAX application is simulated using Tanner 13 tool using a 0.18µm CMOS technology. The current starved VCO is used to improve the linearity and phase noise of PLL. In feedback loop master-slave divided-by-2 frequency divider circuit is used to achieve a maximum speed with minimum power dissipation. The simulation result shows that total power consumption is 3mW at 1.8V power supply at maximum frequency of 2.4 GHz and RMS jitter is 3ps. The locking time of proposed PLL is 300ns, designed PLL is much suitable for WiMAX application

Application for Emu8086 and Proteus in Microcomputer Principle Teaching

Combined with the teaching of Microcomputer Principle and interface technology in electrical engineering and automation, the authors proposes a new teaching method. Firstly, the authors analyzed the teaching and learning situation of Microcomputer Principle and interface technology. Secondly, in the theory and practice teaching process, the authors put forward a new designing scheme that through the Emu8086 and Proteus software for assembly program writing, hardware circuit design and simulation design. The simulation example of frequency divider circuit is constructed by 8086 and 8253A.The experimental results show that the constructed frequency divider circuit can be realized by 8086 simulation. Finally, the authors summarizes the teaching methods of virtual simulation for Emu8086 and Proteus software, and obtains very good teaching results. In this paper, this innovation mode(that is, through the vivid simulation effect) arouse the student's study enthusiasm and provides a new method for embedded curriculum teaching reform.

Design and analysis of the dynamic frequency divider using the BiCMOS–NDR chaos-based circuit

A dynamic frequency divider using a negative-differential-resistance (NDR) circuit combined with an inductor and a capacitor was demonstrated. This NDR circuit was made of Si-based metal-oxide-semiconductor field-effect transistor (MOS) and SiGe-based heterojunction bipolar transistor devices. The operation of this frequency divider circuit was based on the long-period behavior of the nonlinear NDR circuit generating chaos phenomena. This circuit was analyzed by numerical simulation and the results showed that different dividing ratio could be obtained by modulating the input signal frequency using the MATLAB program and the HSPICE program. Some measured results were shown to verify our analyses. This application was designed based on a standard 0.18 μm BiCMOS technique.

A novel pulse swallow based frequency divider circuit for a phase-locked loops

A new and unique frequency divider circuit has been proposed for this work. In this paper, we have implemented a $$\varDelta \varSigma$$ΔΣ fractional-N PLL using a proposed pulse swallow based frequency divider and a programmable prescaler divider circuit. Advantages of the proposed pulse swallow based frequency divider circuit have been illustrated and its usefulness are described in details. This novel pulse swallow based frequency divider technique does not include any reset or reload signal for the swallow counter as it is normally triggered by the SR latch output signal in conventional pulse swallow based frequency divider circuit. Insertion of a variable delay element at the output of the program counter can be eliminated which is normally used to settle the problem of arrival of the falling edge of the swallow counter pulse. In addition, preset enable signal can be generated without any frequency dependent delay generation block and in few cases without selection of any frequency dependent RC network block. The residual phase noise output of the divider at 1 MHz offset frequency is $$-174.5$$-174.5 dBc/Hz for a carrier signal frequency of 4.7 GHz and power consumption is 9 mW from a 1.2 V power supply. The design of the fractional-N PLL has been carried out in 130 nm standard CMOS process. There is no zero division in the proposed frequency divider's swallow counter for any counting state due to the novel mathematical calculating algorithm for the pulse swallow divider circuit.

A 400-mV 2.4-GHz frequency-shift keying transmitter using a capacitor switch across a transformer for a wide tuning range voltage-controlled oscillator

We use a simple directly modulated closed loop to develop a 2.1-mW, 2.4-GHz frequency-shift keying (FSK) transmitter that operates on 400-mV DC supply. Connecting a capacitor bank switch via a transformer in the voltage control oscillator (VCO) to the frequency-divider circuit expands the frequency tuning range without reducing VCO performance. A prototype was fabricated using the 65-nm standard CMOS process with a chip size of 1.65 × 1.85 mm2. A modulation output signal spectrum of −42 dBc at 1.5 MHz with −6 dBm at the PA buffer output terminal; moreover, a VCO phase noise of −101 dBc/Hz at 1 MHz is achieved. The FSK transmitter can readily use voltages supplied by harvested energy because of the low power consumption of the sensor network.

A Modified PFD Based PLL with Frequency Dividers in 0.18-µm CMOS Technology

This paper introduces a modified design of CMOS dynamic Phase Frequency Detector (PFD). The proposed PFD circuit (PPFD) is designed, simulated and the results obtained are analyzed. In order to reduce dead zone, internal signal routing is used in the PPFD circuit. To extend, Phase Locked Loop (PLL) is designed and it is verified with two different Frequency Divider (FD) circuits. There is a decrease in area of the PPFD circuit with 16 transistors and dissipates power of 40.8 pW for 1.2 V power supply. The pre-layout simulation result shows that the PPFD circuit has an elimination of a dead zone. Further, it works with the high speed and reduced power operated in the reference frequency of 50 MHz and the feedback frequency up to 4 GHz.

Dual-Band Waveform Generator With Ultra-Wide Low-Frequency Tuning-Range

This paper presents a novel mixed-signal low-power dual-band square/triangular waveform generator (WFG) chip with a wide low-frequency tuning range for medical bio-electric stimulation therapy. It consists of a relaxation oscillator comprising a hysteresis Schmitt trigger and a timing integrator, along with frequency divider (FD) stages and path selector output for driving an electrode from 16 selectable channels. It was fabricated using Global Foundries 8RF-DM 130-nm CMOS process with a supply voltage of ±1 V for the oscillator and +1 V for logic circuits. The WFG provides an output of around 1.5 $\text{V}_{\textrm {p-p}}$ at a nominal low oscillation frequency of 17 kHz using small-size on-chip passive components of values 10 $\text{k}\Omega $ and 10 pF. The WFG core (band I) can be tuned in the range 6.44–1003 kHz through bias current adjustment, while a lower frequency (band II) in the range 0.1 Hz–502 kHz can be provided digitally through a $\div 2$ stage. The power consumption was only 0.457 mW for the WFG and 2.1 mW for the FD circuit while occupying a total silicon area of only 18 $426~\mu \text{m}^{2}$ .

Wide-locking range LC-tank divide-by-4 injection-locked frequency divider using transformer feedback

A wide locking range, injection locked frequency divider (ILFD) circuit topology is explored. The modulus-four ILFD utilizes a cross-coupled voltage-controlled oscillator in conjunction with transformer feedback, parallel-tuned resonator, and two-segment, series mixers at the injection point. The transformer feedback and two-segment mixing circuit topology achieves a locking range of 2.7 GHz (14.1 to 16.8 GHz) at an injection point bias of 0.9 Vdc and 0 dBm injection power. Spectral measurements at the ILFD output demonstrate proper phase-lock operation and expected phase noise reduction using a high quality signal source at the ILFD input. The ILFD is implemented in the TSMC 0.18 μm 1P6M CMOS process, utilizes a die area of 0.839 × 0.566 mm2 and consumes 16.56 mW. © 2015 Wiley Periodicals, Inc. Int J RF and Microwave CAE 25:557–562, 2015.

22.8 GHz Substrate Integrated Waveguide Analog Frequency Divide-by-3 Circuit

A 22.8 GHz analog frequency divide-by-3 circuit is presented based on an injection locked oscillator. Substrate integrated waveguide (SIW) technology is used to implement the input and output sections of the frequency divider circuit. The input SIW section at the gate of the active device permits the introduction of the injection signal at the third harmonic frequency of the oscillator, while the output section is designed to maximize the DC-RF conversion efficiency of the oscillator circuit. A prototype is fabricated presenting a measured DC-RF efficiency of 38.5% at 7.603 GHz output frequency with 3.7 dBm output power. An injection locking bandwidth of 301.4 MHz was obtained for a 1.5 dBm input injection signal at 22.8 GHz.

A 300 mV sub-threshold region 2.4 GHz voltage-controlled oscillator and frequency divider with transformer technique for ultralow power RF applications

A new ultralow voltage 2.4 GHz voltage-controlled oscillator (VCO) and a divide-by-2 frequency divider circuits operating in a CMOS sub-threshold region using a transformer technique have been developed. In the sub-threshold region, the CMOS transistor high frequency performances are decreased to the point where oscillation and frequency division are challenging to achieve. The new proposed VCO uses the transformer feedback complementary VCO technique to improves VCO negative feedback gain. The circuits have been fabricated in a 65 nm standard CMOS process. The oscillation frequency is designed at 2.4 GHz under a 300 mV supply voltage. The total power consumption is 202 µW with noise performance of −96 dBc/Hz at 1 MHz offset. The new proposed frequency divider circuit consists of two stages master-slave D-type flip-flop (DFF). The DFF differential input is coupled to a transformer circuit instead of transistors to reduce the number of stacks. The minimum operating supply voltage is 300 mV with power consumption of 34 µW with a free-run frequency of 1.085 GHz.

A Novel, Low-Voltage, Current Reused, Quadrature VCO and Divide-by-4 Frequency Divider Circuit

A low-voltage, current-reused, quadrature voltage controlled oscillator (QVCO) and divide-by-4 frequency divider (FD4) architecture is presented for the first time. The proposed architecture features compact and low voltage operation by the proper stacking of a ring-type injection locked FD4 and a back-gate coupled QVCO. This design lowers the power consumption and eliminates the need of high frequency divider as well as buffering stage. The circuit has been implemented in 0.18-μm triple-well CMOS process. Experimental results show a phase noise level of -114.1 dBc/Hz at 1 MHz offset from carrier (2.2 GHz). This chip occupies a core area of 0.9×0.35 mm2 and consumes 2.7 mA from a 1.3 V power supply.

Frequency divider design using the combination of transistors and passive devices

The behavior of a frequency divider circuit using negative differential resistance (NDR) circuit, which is composed of resistor (R) and bipolar junction transistor (BJT), is studied. This frequency divider is mainly made of an R-BJT-NDR circuit, an inductor, and a capacitor. The operation is based on the long-period behavior of the NDR-based chaos circuit. We investigate the effects of the input signal frequency, bias, and amplitude on its operation. The results show that the dividing ratio can be selected by modulating these parameters. Finally, we demonstrate the high-frequency consideration and characteristic of this frequency divider.

Research of Frequency Divider Based on Programmable Logic Device

The design method of general integer and half-integer frequency divider circuits is introduced in this paper. It applies the module and parameterized idea, which can be realized under the FPGA developing platform. According to modifying the specific parameters, it can be applied to the different occasions. The experiment simulation and the result of the apparatus’ testing all get good effect. The generality of this design is good. It can be used into the designs of diverse digital circuit systems.