Frequency Compensation Method Research Articles

Four stage CMOS operational amplifier, frequency compensated via active miller network

AbstractA four‐stage CMOS operational amplifier is proposed in this work. The designed amplifier is frequency compensated via two differential blocks and two Miller capacitors. Unlike well‐known frequency compensation methods, the proposed compensation leaves the output node while exploiting extremely smaller capacitors compared to conventional approaches. The presented approach is modeled symbolically and realized at the circuit level via the Hspice circuit simulator and 0.18 μm CMOS technology. Good agreements between two separate simulation paths verify the validity and accuracy of the proposed approach. Ample simulation results are reported to investigate the proposed amplifier regarding parameter mismatches. According to the simulation results, the proposed four‐stage amplifier is an excellent candidate to be used in larger systems such as data converters, modulators, and sensors while it shows more than 169 dB as DC‐gain, 10 MHz as unity gain frequency with power consumption less than 500 μW.

Novel Data-Aided Carrier Frequency Offset Compensation Methods Using Asymmetric-Shape Constellations for Burst-Mode Coherent Reception

This paper introduces a novel data-aided carrier frequency offset (CFO) estimation and compensation method for m-array phase shift keying (m-PSK) signals in burst-mode digital coherent reception. Its key advances are as follows; the use of newly designed training symbols (TS) that exhibit asymmetric distributed constellations after differential decoding and a vector summation based feed-forward CFO estimation algorithm. These offer short response time and strong robustness to training symbols (TS) timing detection error with wide CFO estimation range of ±B/2, where B is signal baudrate. We evaluate the feasibility of the proposal by simulations of and experiments on 12.5-Gbaud SP-QPSK signals that target optical budget enhancement of 25-Gbps/λ-class PONs to realize long-reach and high splitting ratio optical access. The 100-km burst-mode transmission experiments confirm the proposal offers high sensitivity detection of better than −43 dBm with much wider CFO range of above ±10 GHz.

Double Differential Blocks Based Frequency Compensation: A Four-Stage CMOS Amplifier

In this paper, an efficient frequency compensation method is investigated for a four-stage CMOS amplifier. The frequency compensation network includes two sets of capacitors at the differential block output. The proposed compensated amplifier is described symbolically to obtain the transfer function. Meanwhile, the proposed configuration is designed at the circuit level and is simulated via 0.18[Formula: see text][Formula: see text]m CMOS technology. Compared to the other existing methods, the proposed amplifier satisfies the figure of merits considerably. This stems from the fact that lower capacitor values are used to perform compensation, leading to lower die occupation, and reach boosted gain bandwidth products. Leveraging both the configuration and design procedure, a high-performance four-stage is presented in this paper.

Miller’s Compensation Techniques for a High Gain, High BW OP-AMP at 65 nm Technology

OP-AMPs find applications in different domains of electronics engineering including communications. There have been several OP-AMP configurations realized in the last decades for different target applications. But with the evolution of communication standards, to meet the demand for high data rate over the years, the requirement for a high frequency and high BW OP-AMP is gaining attention. This makes the design challenge much higher. This paper presents a two-stage CMOS amplifier that uses a frequency compensation method to facilitate higher BW. Different parameters like Gain, Gain bandwidth product (GBWP), Phase Margin, and Total Power dissipation are considered in this design. A step-by-step procedure for an efficient amplifier design is followed using frequency compensation. We have achieved a gain-bandwidth product (GBWP) of 110 MHz that is capable of driving large capacitive loads. It also achieves 77.7 dB gain and phase margin of 60° with the minimal noise of 2.27 μ^V/√ Hz and the slew rate of 20.12 V/ms

An ACF

With the development of the Internet of Things (IoT) technology, more and more occasions require security protection under extreme resource-constrained conditions. The traditional PUF is difficult to function effectively and requires replacement of equipment, which leads to increased product design and time costs. To tackle these problems, we propose a Software Physical Unclonable Functions (SPUF) scheme based on the high robustness of the RISC-V processor. The main contribution is to utilize the low-voltage feature so that the RISC-V processor operates in an unusual state for generating abnormal information, and to use this information to characterize the chip characteristics. Meanwhile, the frequency compensation method is proposed to further optimize the robustness of the SPUF response, and a lightweight SPUF-based authentication protocol is adopted to improve the authentication security. In this way, the safety and reliability of the proposed PUF are evaluated. The experimental results show that the SPUF data passed the National Institute of Standards and Technology (NIST) randomness tests, with an autocorrelation less than 0.03 at 95% confidence level. The averaged Hamming weight and Hamming distance are 0.495 and 0.501, respectively, making it widely applicable to IoT security.

Full Physical Layer Simulation Tool to Design Future 77 GHz JCRS-Applications

Vehicular communication systems get more and more attention with the upcoming fifth and sixth generation. Hereby, the focus lies on the development of the co-design or co-existence of communications and sensing. So called joints communications and radar sensing systems are seen as one key technology of 6G. As joint systems will have shared waveforms and hardware platforms, there is a huge benefit in cost and space which is one essential argument for the automotive industry. However, to design such a system for new applications like platooning or intersection assistance a physical layer has to be set up to represent the real physical layer properly. The proposed system design closes the lack of such a simulation tool and allows for full physical layer simulations, including e.g. the hardware non-idealities and the channel model for 77GHz. The whole signal processing chain of the physical layer is built up and will be integrated in the higher layer state-of-the-art simulation frameworks like Veins or Artery in the next step. The communications design is developed in Simulink, whereas the sensing part is discussed. The proposed communications architecture covers several transmission approaches (serial, parallel), a CDMA based spreading, a radio frequency representation, the channel (simulated in a 3D-Ray-Tracing-tool) and the receiver structure (e.g. the synchronisation or the channel estimation). Several design criteria are discussed, like the serial or parallel design architecture, the maximum ratio combining or the phase and frequency compensation method. The whole system architecture is freely available (<uri>https://doi.org/10.5281/zenodo.6482565</uri>) and in consequence, the different signal blocks and parameters can be enabled or disabled for evaluations according to future design criteria requirements.

A High Gain, High BW OP AMP with Frequency Compensation Techniques at 65 nm Technology

OP-AMPs finds applications in different domains of electronics engineering including communications. There has been several OP-AMP configurations realized in the last decades for different target applications. But with the evolution of communication standards, to meet the demand for high data rate over the years, requirement for a high frequency and high BW OP-AMP is gaining attention. This makes the design challenge much higher. This paper presents a two-stage CMOS amplifier which uses frequency compensation method to facilitate higher BW. Different parameters like Gain, Gain band width product (GBWP), Phase Margin and Total Power dissipation are considered in this design. A step-by-step procedure for an efficient amplifier design is followed using frequency compensation. We have achieved a gain-bandwidth product (GBWP) of 110 MHz that is capable of driving large capacitive loads. It also achieves 77.7 dB gain with a phase margin of 60o.

A Low Walk Error Analog Front-End Circuit With Intensity Compensation for Direct ToF LiDAR

An analog front-end (AFE) circuit comprising an amplifier module, a peak detector, and a timing discriminator has been designed to facilitate the target identification for direct time-of-flight (dToF) LiDAR. The amplitude saturation error (ASE) is compensated in this article for the intensity determination, which is conducted based on the combination of the pulse width and peak detector. Together with the improved walk error compensation scheme, the proposed AFE circuit can attain the distance and intensity information simultaneously with lower cost and larger dynamic range. A specific frequency compensation method is proposed with a shunt feedback TIA, which improves the stability and mitigates the impact of the package parasitics. The measured -3-dB bandwidth, transimpedance gain, and the input-referred noise current are 281 MHz, 86 dB <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> , and 4.68 pA/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\surd $ </tex-math></inline-formula> Hz respectively. The proposed AFE circuit, which is fabricated in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18~\mu \text{m}$ </tex-math></inline-formula> CMOS technology, achieves the distance accuracy of ±30 ps and the intensity accuracy of ±4% in the dynamic range of 1:5000 without gain control scheme.

Direct Single-Power-Conversion Bidirectional Grid-Connected Inverter Solving Commutation Problem

This article presents a novel direct single-power-conversion bidirectional grid-connected inverter for solving the commutation problem and a control strategy for it. The proposed inverter directly interfaces with a low-voltage battery and grid with only one power conversion stage and performs a bidirectional power conversion. The reliability of the proposed inverter is improved because the commutation capacitor eliminates the commutation problem by providing commutation paths in any switching case. The frequency compensation method converts the nonlinear power transfer characteristic into linear and makes grid current control easy. Furthermore, the interdependence of three control variables enables the control of the grid current using a simple equation. The proposed dual-mode control strategy increases the power capacity of the proposed inverter without increasing the turns ratio and decreasing the leakage inductance. The conduction losses can be reduced using this strategy. Additionally, the ZVS capability reduces the switching losses. These features of the proposed inverter and its control strategy enable the proposed inverter to achieve high efficiency and power quality with a simple structure. The theoretical concepts of the proposed inverter were experimentally verified using a 1-kW prototype.

Dual Active-Feedback Frequency Compensation for Output-Capacitorless LDO With Transient and Stability Enhancement in 65-nm CMOS

An output-capacitorless low-dropout regulator (OCL-LDO) using a dual-active feedback frequency compensation (DAFFC) scheme with both transient and stability enhancement has been presented in this paper. The DAFFC scheme consists of two parallel active feedback paths, which creates two pole-zero pairs to effectively enhance the stability and transient response for the proposed OCL-LDO. Compared to the conventional single-path active-feedback frequency compensation method, the proposed DAFFC technique has provided one more design freedom with one more active feedback loop deployed and has been proved to be capable of obtaining better compensation effects with the same capacitor budget. Besides, the induced extra ac currents by the two active feedback loops have also enhanced the transient response of the proposed OCL-LDO. To substantiate the proposed DAFFC, a telescopic cascode output stage for error amplifier, and two on-chip compensation capacitors (5 and 1 pF, respectively) are needed. The proposed OCL-LDO has been implemented in 65-nm CMOS technology and the active chip area is 0.0105 mm2. The output voltage is 0.8 V, and the minimum input voltage is 0.95 V at 100-mA loading current. The proposed OCL-LDO can work stably in a load range of 0 to 100 mA with 14-μA quiescent current.

Design, Optimization, and Compensation of a High-Precision Single-Excitation Absolute Capacitance Angular Encoder up to ±4$^{\prime\prime}$

This paper presents a single-excitation absolute capacitive rotary encoder that is small in size, lightweight, robust, and highly precise. The encoder consists of two plates: a rotor and a stator. The rotor consists of a planar coupling ring, a petal-form sensitive electrode, and a rough sensitive electrode, whereas the stator consists of a planar excitation ring and eight groups of collection electrodes. First, the two sensitive electrodes together with the eight sets of collection electrodes encode the angular position into amplitude-modulated signals, which are read out by a single-excitation electronic system. High-precision absolute position information is obtained by using the combination of 36 petal-form sensitive electrodes and a rough sensitive electrode. Then, a linear programming method is used to optimize the critical dimensions of the encoder within a limited area to achieve a miniaturized design. Finally, a harmonic frequency compensation method is used to reduce repeatable and periodical measurement errors, which are caused by manufacturing, circuit, and installation errors. A prototype is fabricated and tested on a high-precision testing turntable. The measurement results show that the resolution is 0.00015° and the accuracy over the full absolute range is 0.0022°, indicating that the encoder has considerable potential for use in high-precision applications.

Improved reversed nested miller frequency compensation technique based on current comparator for three-stage amplifiers

This paper attempts to propose a newly modified method to improve the frequency compensation of three-stage operational trans-conductance amplifiers. In the topology of the new frequency compensation, a current comparator is placed on the feedback path, while the common node of Miller compensation capacitors, the feedforward path, is removed by eliminating the right-half plane zero. This tremendously improves the phase margin, stability, and gain band width product. Compared with other available frequency compensation methods, the newly proposed method manages to improve the figure of merits and lower power consumption while significantly decreasing the dimensions of capacitors in the compensation network. The superiority of the new method over other conventional methods for reversed nested Miller compensation has been examined by a three stage amplifier that has been designed and simulated through a 180 nm standard library CMOS. The results indicate that the new amplifier has achieved a power consumption of 285 µW, gain band width product of 14 MHz, and phase margin of 86° with 100 pF capacitance load at the supply voltage of 1.8 V.

Fully Differential Single Resonator FM Gyroscope Using CW/CCW Mode Separator

This paper reports a fully differential frequency modulated (FM) gyroscope where the superposed clockwise (CW) and counter clockwise (CCW) modes are independently controlled on a single resonator. The CW and CCW mode detectors were developed to control both modes simultaneously on the resonator. A frequency and quality factor mismatch compensation method was developed to perfectly orthogonalize these two modes. A FM gyroscope operation with excellent linearity between applied angular rate and frequency difference was demonstrated. The temperature coefficient of scale factor was as small as −52 ± 136 ppm/°C. The scale factor and bias were stable over 700 hours with the drift less than 0.062 ± 0.100 ppm/hr and 31 ± 121 ppm/hr, respectively. [2018-0103]

계단 주파수 레이더에서 VMD 방식을 이용한 이동표적의 속도 추정 및 도플러 주파수 보상 기법 분석

계단 주파수 레이더에서 VMD 방식을 이용한 이동표적의 속도 추정 및 도플러 주파수 보상 기법 분석

Optimal Design Methodology for Frequency Compensation Circuits in Logging Cable Transmission Channel

Bandwidth limitation is a vital problem for high-speed data transmission in logging cable telemetry systems (LCTSs). This paper proposes a frequency compensation method with an analog circuit design, possessing high flexibility and robustness. Analytical expressions are derived for the relationship between pole-zero and gain, deviations caused by high temperature; and are then verified via simulation. To address the efficacy of the circuit design, a real case with low computation complexity and high accuracy is proposed and employed. The case of a 7[Formula: see text]km LCTS shows frequency compensation with a 200% bandwidth expansion — from 160[Formula: see text]kHz at [Formula: see text]55[Formula: see text]dB of the original cable to 300[Formula: see text]kHz at [Formula: see text]3[Formula: see text]dB — and a 60[Formula: see text]dB improvement in high frequency gain. After comparing the signals with and without compensation, the improvements in transmission performance by the proposed pre-emphasis circuit and equalizer are confirmed.

A robust low quiescent current power receiver for inductive power transmission in bio implants

ABSTRACTIn this paper, a robust low quiescent current complementary metal-oxide semiconductor (CMOS) power receiver for wireless power transmission is presented. This power receiver consists of three main parts including rectifier, switch capacitor DC–DC converter and low-dropout regulator (LDO) without output capacitor. The switch capacitor DC–DC converter has variable conversion ratios and synchronous controller that lets the DC–DC converter to switch among five different conversion ratios to prevent output voltage drop and LDO regulator efficiency reduction. For all ranges of output current (0–10 mA), the voltage regulator is compensated and is stable. Voltage regulator stabilisation does not need the off-chip capacitor. In addition, a novel adaptive biasing frequency compensation method for low dropout voltage regulator is proposed in this paper. This method provides essential minimum current for compensation and reduces the quiescent current more effectively. The power receiver was designed in a 180-nm industrial CMOS technology, and the voltage range of the input is from 0.8 to 2 V, while the voltage range of the output is from 1.2 to 1.75 V, with a maximum load current of 10 mA, the unregulated efficiency of 79.2%, and the regulated efficiency of 64.4%.

An effective sampling clock synchronization method for continuous- and burst-mode transmission in OFDMA-PONs

A sampling frequency offset (SFO) estimation and compensation method based on frequency domain correlation of long training symbols for orthogonal frequency division multiple access passive optical network (OFDMA-PON) is experimentally demonstrated, which shows excellent performances in transmissions of continuous- and burst-mode. For continuous-mode transmission under a certain SFO, the proposed scheme can perform effectively in a wide received optical power (RoP) range from −8dBm to −2dBm and has high estimation veracity and a large applicable range as large as 100ppm at a certain RoP. Similar behavior is also demonstrated under burst-mode transmission with tiny performance degradation caused by the fact that the algorithm needs time to reach a stable status of synchronization.

Rubidium chip-scale atomic clock with improved long-term stability through light intensity optimization and compensation for laser frequency detuning

We demonstrate the implementation of a Rb87 chip-scale atomic clock (CSAC) that has improved long-term stability. A simple method of reducing the frequency drift in the CSAC is proposed. As well as the well-known effect of light intensity on the clock frequency, our analysis shows that the frequency drift that is due to laser frequency detuning (LFD) variation originates from asymmetry in the coherent laser fields, and thus, we propose to actively compensate the clock frequency by using variations in the light intensity and LFD. We performed experiments to obtain precise clock frequency sensitivities to the light intensity and LFD, and the frequency drift was reduced from 7.1×10−11/day to 6.9×10−13/day with the frequency compensation method. Additionally, the CSAC with an optimized configuration of light intensity and microwave power showed evident long-term frequency stability improvement, from 8.9×10−11 to 8.7×10−12 at 105 s. Therefore, our method is useful in reducing the frequency drift of CSACs and could be potentially used in applications that require moderate long-term stability of sub-1×10−11.

Design Procedure for Three-Stage CMOS OTAs with AC Boosting Frequency Compensation Technique

ABSTRACTAn analytic design guide to design a three-stage cascade CMOS operational amplifier compensated by AC boosting frequency compensation (ACBC) method is presented in this paper. The procedure allows electrical parameters such as gain bandwidth (GBW) product or phase margin to be related to the value of circuit elements such as aspect ratio or biasing currents of transistors. The presented design guide is suited for pencil-and-paper design and yields accurate performance without unnecessary circuit constraint introduction. Simulation results using TSMC 0.18 µm CMOS process verifies accuracy and robustness of proposed procedure. Various load capacitors and circuit conditions are simulated and, based on obtained results, the presented design guide is comprehensive and efficient since it leads us from frequency response parameters to aspect ratio of MOSFETs.

基于频率补偿的窄脉冲量子级联激光器快速驱动技术

The line width of pulsed quantum cascade lasers(QCL) increases with the device heating up during the driving pulse, so QCL drivers need to generate ultra-short current pulse. Generally, pulses of 5 ns to 15 ns durations can reach the Fourier transform limit. However, due to the existence of parasitic parameters, narrow pulses will lead to overshoot or oscillation. Therefore, the current commercial QCL drivers can not meet this requirement. To obtain narrower line width of QCLs, a frequency compensation method based on conventional pulse constant current circuit was proposed in this work to eliminate overshoot and oscillation. And a stable pulse laser driving circuit was also designed which can output 0-2 A pulse current, with 8.4-200 ns pulse width, 4 ns rising time, and 1% overshoot. Function test was carried out with a QCL with 4.6m center wavelength made from Institute of Semiconductor of Chinese Academy of Sciences, and a Fourier transform infrared spectroscopy. The laser line width decreased almost linearly from 0.35 cm-1 to 0.12 cm-1, when the driving pulse width decreased from 100 ns to 10 ns. Experimental results show that the driver is able to output stable narrow pulses, which is suitable for narrow line width driving of QCLs and their applications.