Frequency Clock Generation Research Articles

Design and Analysis of Ultra-low Power Voltage Controlled Oscillator in Nanoscale Technologies

In latest wired and wireless communication equipment, VCO (voltage-controlled oscillator) is the major building block and particularly used as the stable high frequency clock generator. VCO performance is measured through frequency range, power supply used, area occupied, power consumption, delay, and phase noise. VCO is the cascaded of odd number of inverter stages in a ring format, hence it is also articulated as a ring oscillator. Today’s portable communication devices are battery operated. Hence, low power and area efficient designs play a key role in battery life enhancement and device size reduction. Device scaling improves the effective silicon area utilization, but it leads to more leakages. Therefore, low power techniques along with the technology scaling is the best way of low power designs. In this article, discussed various low power schemes. The ring oscillator designs are carried out in various nano meter scaled technologies such as 180nm, 90nm,65nm and 45nm. A 5-stage ring oscillator is implemented in each technology along with low power schemes, simulated in Cadence virtuoso, and noted power, delay, and area. Observed that the proposed ring oscillator with sleepy keeper technique generated a stable frequency of oscillations in the range of 1GHz-2GHz. A control voltage of 1.8V to 0.4V is applied and targeted the power less than 30mW and delay in 0.25p sec.

An Event-Driven Self-Clocked Digital Low-Dropout Regulator with Adaptive Frequency Control

Digital low-dropout (DLDO) is widely used for power management in the system-on-chip (SoC) because of its low-voltage operation and process scalability. However, conventional DLDOs suffer from the trade-off between transient response and power consumption of the DLDO and the clock generator. This paper proposes an event-driven self-clocked DLDO regulator. The proposed low quiescent current (IQ) event-driven adaptive frequency clock generator (EACG) adapts its frequency in different load conditions without a current sensor or complex compensation circuit for stable operation in the entire load range. The proposed DLDO does not need any external clocking signal and can maintain low output ripple and low power consumption in the steady-state. The clock-less transient detector (CLTD), consisting of two clock-independent transient detection paths, uses power more efficiently and improves the transient response significantly without sacrificing the power consumption. This work was fabricated in a 40 nm CMOS process with an 0.3 nF on-chip capacitor. The measurement results show that with the step load current between 1 mA and 60 mA, the proposed DLDO achieves a transient recovery time of 220 ns. The total IQ of the proposed DLDO is only 26 μA in steady-state, and it achieves stable operation in the entire load range.

Design of double ring lock ring in extensible frequency clock generator chip

With the continuous development of computer technology and the continuous improvement of interface data rate, the clock frequency has reached the demand of several gigahertz, which makes the electromagnetic interference problem very serious. Spread spectrum clock is an effective method to reduce electromagnetic interference of digital chips. Therefore, this paper designs a double-loop phase-locked loop that can spread spectrum and has strong anti-electromagnetic noise interference ability. The designed dual-loop phase-locked loop can be used in the clock generator chip. The overall structure of the circuit consists of a main loop and a secondary loop. The main loop is an adjustable phase-locked loop circuit that can provide an output with a center frequency of 500MHz. The secondary loop can realize the spread spectrum function by charging and discharging the filter capacitor of the main loop loop, and at the same time, the spreading depth can be set by the feedback based on the frequency division. The dual-loop phase-locked loop designed in this paper has a good effect in spread spectrum and anti-electromagnetic interference noise.

Low power frequency doubler

A low power frequency doubler circuit that only requires standard CMOS logic gates and on-chip passive components is proposed. The proposed circuit is shown to be compact and has been validated with FPGA implementation. The proposed circuit is found to be robust to wide frequency range and supply voltage variations with excellent frequency and phase performance on high frequency clock generation.

Enhanced Digital Synthesized Phase Locked Loop with High Frequency Compensation and Clock Generation

The proposed work concentrates on the integration of an 8-GHz voltage-controlled oscillator (VCO) and a frequency tripler for 24-GHz local oscillator generation. By stacking the VCO and the tripler with a current-reused topology, the power consumption of this integration can be saved. The proposed circuit with a total chip area of 0.7 mm ×0.8 mm is implemented in a 0.18 μm CMOS process. As the tuning voltage increases from 0 to 2 V, the measured frequency tuning range (FTR) of the VCO is from 7.06 to 8.33 GHz. The final resulting output frequency from the tripler ranges from 21.18 to 24.98 GHz (16.5% FTR). The core circuit totally consumes 5 mA from a 1.8-V supply voltage. The measured phase noises at the VCO and frequency tripler outputs are − 113.76 and − 105.1 dBc/Hz at 1-MHz offset frequency, respectively, when Vtune is 0 V. The best evaluated figure of merit with tuning is − 187.2 dBc/Hz (decibels relative to carrier). Closed form equations allow for a performance driven design for both PLL and estimator. By using a variable sample frequency controlled by the PLL, the Kalman filter is always operated around its center frequency, which is the rated grid frequency. The new topology is compared to other published single-phase PLL designs and its operation is verified by both simulations and experiments. This integration of a VCO and a frequency tripler exhibits a high potential for the use in low-power 24-GHz phase-locked loops. The PLL designed using dual mode logic technique exhibits excellent performance even under severely distorted utility grid voltage conditions. This robustness makes it very suitable for use in systems connected to grids having an important share of non-linear loads.

Stability of charge-pump phase-locked loops: the hold-in and pull-in ranges

Abstract The problem of design and analysis of synchronization control circuits is a challenging task for many applications: satellite navigation, digital communication, wireless networks, and others. In this article the Charge-Pump Phase-Locked Loop (CP-PLL) electronic circuit, which is used for frequency synthesis and clock generation in computer architectures, is studied. Analysis of CP-PLL is not trivial: full mathematical model, rigorous definitions, and analysis still remain open issues in many respects. This article is devoted to development of a mathematical model, taking into account engineering aspects of the circuit, interpretation of core engineering problems, definition in relation to mathematical model, and rigorous analysis.

A wideband receiver front-end using 1st and 3rd harmonics of the N-path filter response

Harmonic selectivity and inaccessibility to accurate low-power high frequency clock generator are two main imperfections in the tunable N-path filters. In this paper, conventional N-path filter and conventional harmonic rejection (HR) N-path architectures are analyzed, and related equations are derived and are verified by simulation results. Furthermore, a wideband tunable receiver front-end using HR N-path switching systems is proposed. Using third harmonic of filter response instead of fundamental harmonic, the required input clock frequency in the multi-phase clock generator is decreased by a factor of three. The receiver front-end benefits low and high frequency bands. At low frequency band (0.4–1.2 GHz) the first harmonic, and at high frequency band (1.2–3.3 GHz) the third harmonic of filter response are selected and are downconverted to the baseband frequency. The structure is designed and is simulated using CMOS-90 nm technology in schematic level. The total power consumption and $$S_{11}$$ are $$<27.14$$ mW and $$-13.5$$ dB, respectively. Furthermore, NF at low and high frequency bands are 2.56 and 3.53 dB, respectively.

A 0.13 μm CMOS System-on-Chip for a 512 × 424 Time-of-Flight Image Sensor With Multi-Frequency Photo-Demodulation up to 130 MHz and 2 GS/s ADC

We introduce a 512 × 424 time-of-flight (TOF) depth image sensor designed in a TSMC 0.13 μm LP 1P5M CMOS process, suitable for use in Microsoft Kinect for XBOX ONE. The 10 μm × 10 μm pixel incorporates a TOF detector that operates using the quantum efficiency modulation (QEM) technique at high modulation frequencies of up to 130 MHz, achieves a modulation contrast of 67% at 50 MHz and a responsivity of 0.14 A/W at 860 nm. The TOF sensor includes a 2 GS/s 10 bit signal path, which is used for the high ADC bandwidth requirements of the system that requires many ADC conversions per frame. The chip also comprises a clock generation circuit featuring a programmable phase and frequency clock generator with 312.5-ps phase step resolution derived from a 1.6 GHz oscillator. An integrated shutter engine and a programmable digital micro-sequencer allows an extremely flexible multi-gain/multi-shutter and multi-frequency/multi-phase operation. All chip data is transferred using two 4-lane MIPI D-PHY interfaces with a total of 8 Gb/s input/output bandwidth. The reported experimental results demonstrate a wide depth range of operation (0.8–4.2 m), small accuracy error ( $ 1%), very low depth uncertainty ( $ 0.5% of actual distance), and very high dynamic range ( $>$ 64 dB).

A 0.6-V 8.3-ENOB asynchronous SAR ADC for biomedical applications

A microwatt asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) is presented. The supply voltage of the SAR ADC is decreased to 0.6 V to fit the low voltage and low power requirements of biomedical systems. The tail capacitor of the DAC array is reused for least significant bit conversion to decrease the total DAC capacitance thus reducing the power. Asynchronous control logic avoids the high frequency clock generator and further reduces the power consumption. The prototype ADC is fabricated with a standard 0.18 μm CMOS technology. Experimental results show that it achieves an ENOB of 8.3 bit at a 300-kS/s sampling rate. Very low power consumption of 3.04 μW is achieved, resulting in a figure of merit of 32 fJ/conv.-step.

PREDICTING THE JITTER OF PLL–DLL BASED FREQUENCY SYNTHESIZERS

Phase Lock Loop (PLL) and Delay Locked Loops (DLLs) are major analog circuits used for many different communication applications such as frequency synthesizer, radio, computer, clock generation and recovery, global positioning system etc. This paper developed a methodical approach to calculate jitter of the PLL and DLL. The methodological nature of our approach would manifest itself in the development of a clear step-by-step procedure for the design of the constituent components of the same. Finally, jitter of DLL has been reduced by proposed technique.

A low power, low jitter DLL based low frequency (250 kHz) clock generator

Digital Delayed Locked Loop (DLL)-based clock generation has proven itself a viable alternative in today’s clock design segment over the traditional Phase Locked Loop (PLL)-based design by offering lower design complexity with satisfying low power budget. In this paper, a novel design of an on-chip clock generator of very low frequency of 250 kHz and 50% duty cycle using a DLL has been presented. The worst-case jitter produced by the clock is only 11.3 ns. The clock has rise time and fall time of 164.39 ps and 123.7 ps (on an average), respectively, with a glitch of 6 mV. The clock produces a very low power of 3.92 mW. The design was implemented under 180 nm process technology and assuming 1.8 V power supply.

A Design of High Frequency Clock Generation Circuit

A clock generation circuit is proposed based on CMOSFET technology, which is comprised of a reference voltage source, a common source voltage amplifier, voltage controlled oscillator and timing circuit. By which a particular clock is produced, whose duty cycle is less than 50%. It is used 0.5 μ s CMOS process, HSPICE simulation results indicates that the average frequency of clock signal is 2.071MHz, and the average duty cycle is 31.565% .

A multiple frequency clock generator using wide operation frequency range phase interpolator

This paper presents a multiple frequency clock generator that is composed of the wide operation frequency range phase interpolator and the phase combiner. The wide operation frequency range phase interpolator is developed using a delay-time-adjustment phase interpolator (DTAPI) circuit with various oscillation frequencies for different clock domain applications. The phase combiner generates multiple clock frequencies through various phase combination inputs generated by the preceding proposed phase interpolators. The varying output transition delay time of the proposed DTAPI is the result of the various oscillation frequencies of the voltage-controlled oscillator. The test chip was fabricated in a 0.18μm CMOS process with a 1.8V supply voltage. The measured phase noise and power dissipation are −87.28dBc/Hz at 1MHz offset frequency from 88.8MHz and 1.32mW, −77.47dBc/Hz and 2.06mW from 797.8MHz, respectively. The duty cycle error rate of the output clock frequency is less than 1.5%.

ZeROA: Zero Clock Skew Rotary Oscillatory Array

Resonant rotary clocking is a clocking technology for high frequency clock generation and distribution at a low power dissipation rate. It is commonly conceived that the multiple phases on the rings of the rotary oscillatory array (ROA) necessitate a non-zero clock skew operation. In this paper, the feasibility of zero clock skew synchronization with the rotary clocking technology implemented on the ROA is shown. Design automation experiments are performed to demonstrate that the zero clock skew operation can be achieved with minimal change in the performance of rotary clock operation. In particular, a marginal ±1.5% change in the tapping wirelength and a negligible 0.38% average skew mismatch are reported in experiments on R1-R5 and ISPD 2010 benchmark circuits.

A 800μW 1GHz Charge Pump Based Phase-Locked Loop in Submicron CMOS Process

A 800μW 1GHz Charge Pump Based Phase-Locked Loop in Submicron CMOS ProcessDemand of modern measurement systems in submicron CMOS process introduced new challenges in design of low power high frequency clock generation systems. Technical possibilities for clock generation using classical oscillator based on a quartz filter is limited to tens of megahertz. Thus, 1 GHz clock generation is not possible without a frequency multiplier system. It is difficult to achieve, because in submicron process, where the integration of analog and digital blocks poses serious challenges. The proposed solution is a low power charge pump phase-locked loop (CPPLL) with the center frequency of 1 GHz. It combines various modern circuit techniques, whose main aim is to lower power consumption, which is below 800 μW for the whole PLL, while maintaining good noise properties, where the jitter rms is 8.87 ps. The proposed phase-locked loop is designed in 0.18 μm CMOS process.

Design and Implementation of a High Speed Modulation System for Space Applications

为了适应空间科学技术的发展, 满足空间科学应用系统的数据传输速率、多进制数字调制方式以及实现调制体制灵活性的要求, 提出了一种适用于空间应用的高速调制系统的设计与实现方案. 该方案采用了基于FPGA和DAC的通信调制技术, 可在硬件设计不变的情况下, 实现QPSK, 8 PSK和16 QAM等多种调制方式下的高速数据传输. 分析了高速调制在硬件实现上的技术难点, 解决了高频率高精度同步时钟生成、高速数据转换、宽带调制等技术问题. 实测表明, 在载频为2 GHz时, 该调制系统在8PSK调制下速率可达750 Mbit/s, 且调制信号的矢量幅度误差(EVM)仅为3.3 %.