Frame Error Rate Performance Research Articles

Parallel Implementation of K-Best Quadrature Amplitude Modulation Detection for Massive Multiple Input Multiple Output Systems

Massive MIMO (Multiple Input Multiple Output) systems impose significant processing burdens along with strict latency requirements. The combination of large-scale antenna arrays and wide bandwidth requirements for next-generation wireless systems creates an exponential increase in frontend to backend data. Balancing the processing latency and reliability is critical for baseband processing tasks such as QAM detection. While linear detection algorithms have low computational complexity, their use in Massive MIMO scenario has heavy degradation in error performance. Nonlinear detection methods such as Maximum Likelihood and Sphere Decoding have good error performance, but they suffer from high, variable, and uncontrollable computational complexity. For such cases, the K-best QAM detection algorithm can provide required control over the system performance while maintaining near-ML error performance. In this paper, hard-output, as well as soft-output K-best QAM detection, is implemented in a CPU by utilizing the multiple cores combined with vector processing. Similarly, hard-output detection in a GPU is implemented by leveraging the SIMD (Single Instruction, Multiple Data) architecture and Warp-based execution model. The processing time per bit and the energy consumption per bit are compared for CPU and GPU implementations for QAM constellation density and MIMO array size. The GPU implementation shows up to 5× processing latency per bit improvement and up to 120× energy consumption per bit improvement over the CPU implementation for typical QAM constellations such as 4, 16, and 64 QAM. GPU implementation also shows up to 125× improvement over CPU implementation in energy consumption per bit for larger MIMO configurations such as 24 × 24 and 32 × 32. Finally, the soft-output detector is combined with a LDPC (Low-Density Parity Check) decoder to obtain the FER (Frame Error Rate) performance for CPU implementation. The FER is then combined with frame processing latency to form a Goodput metric to demonstrate the latency and reliability tradeoff.

Finite-Length Scaling of SC-LDPC Codes With a Limited Number of Decoding Iterations

We propose four finite-length scaling laws to predict the frame error rate (FER) performance in the waterfall region of spatially-coupled low-density parity-check code ensembles under full belief propagation (BP) decoding with a limit on the number of decoding iterations and a scaling law for sliding window decoding, also with limited iterations. The laws for full BP decoding provide a choice between accuracy and computational complexity; a good balance between them is achieved by the law that models the number of decoded bits after a certain number of BP iterations by a time-integrated Ornstein-Uhlenbeck process. This framework is developed further to model sliding window decoding as a race between the integrated Ornstein-Uhlenbeck process and an absorbing barrier that corresponds to the left boundary of the sliding window. The proposed scaling laws yield accurate FER predictions for the semi-structured code ensembles proposed by Olmos and Urbanke.

Decoding LDPC Codes by Using Negative Proximal Regularization

The low-density parity-check (LDPC) decoding problem can be expressed as an integer linear programming (ILP) problem. One efficient method to solve the ILP problem is to relax the integer constraints and add penalty terms to the objective function, and the revised problem can be solved via the alternating direction method of multipliers (ADMM) algorithm. These penalty terms can punish the non-integral solutions and improve the decoding performance of the decoder. However, ADMM decoders are easily trapped in a local solution, which limits the frame error rate (FER) performance of the decoders at low signal-to-noise ratios (SNR). In this paper, we propose a restartable ADMM-based decoder using a negative proximal regularization. The negative proximal term will be updated whenever the decoder finds a new local solution. Therefore, the decoder can be restarted several times and the candidate solution which satisfies the parity-check equations and has the lowest objective function value can be selected as the decoder’s output. Some properties, together with several choices of penalty terms are discussed. We also investigate the convergence of our proposed decoder, and prove that the possibility of decoding errors is independent of the codeword that is transmitted. Simulation results show that our proposed decoder outperforms other ADMM-based decoders in most cases, while the decoding complexity maintains the same.

3GPP 5G V2X Error Correction Coding for Various Propagation Environments: A QoS Approach

Vehicle-to-everything (V2X) communications is an emerging branch of wireless communications and has recently gained a lot of interest not only from academia but also from the automotive and telecommunications industry. An important feature of V2X telecommunication systems is that the communication quality varies quickly in time due to the high mobility of the transceivers and due to the rapid change in the fading characteristics of the communication medium. For this reason, it is vital to maintain tolerable quality of service (QoS) in a V2X communication environment, in terms of communication reliability, power, end-to-end latency, data rate, communication range, throughput and vehicle density. A significant impact on the quality parameters of the system has been the coding scheme used by the V2X telecommunication system. For this purpose, we examine the effect that popular coding schemes have on the QoS of a V2X communication system. More specifically, the impact of fourth-generation long-term evolution (4G-LTE) turbo codes, fifth-generation new radio (5G-NR) polar codes and 5G-NR low-density parity-check codes (LDPC) on the QoS parameters of a V2X communication system is researched. Το this end, we employ stochastic V2X propagation models that simulate every possible V2X channel state and traffic environment, based on the third-generation partnership project (3GPP) Release 16 specifications. These propagation models form the basis of our study, since through them, at a first level, we analyze the frame error rate (FER) performance for different levels of signal-to-noise ratios (SNRs) for all the aforementioned coding schemes and 128-bit V2X-compatible data frames, and, at a second level, we investigate the impact of these propagation models and coding schemes on the V2X QoS parameters. Our analysis shows that turbo-based coding schemes satisfy all the QoS parameters and achieve overall communication quality comparable to polar and better than LDPC, making them suitable for small-frame 5G V2X services.

Predictive Precoder Design for OTFS-Enabled URLLC: A Deep Learning Approach

This paper investigates the orthogonal time frequency space (OTFS) transmission for enabling ultra-reliable low-latency communications (URLLC). To guarantee excellent reliability performance, pragmatic precoder design is an effective and indispensable solution. However, the design requires accurate instantaneous channel state information at the transmitter (ICSIT) which is not always available in practice. Motivated by this, we adopt a deep learning (DL) approach to exploit implicit features from estimated historical delay-Doppler domain channels (DDCs) to directly predict the precoder to be adopted in the next time frame for minimizing the frame error rate (FER), that can further improve the system reliability without the acquisition of ICSIT. To this end, we first establish a predictive transmission protocol and formulate a general problem for the precoder design where a closed-form theoretical FER expression is derived serving as the objective function to characterize the system reliability. Then, we propose a DL-based predictive precoder design framework which exploits an unsupervised learning mechanism to improve the practicability of the proposed scheme. As a realization of the proposed framework, we design a DDCs-aware convolutional long short-term memory (CLSTM) network for the precoder design, where both the convolutional neural network and LSTM modules are adopted to facilitate the spatial-temporal feature extraction from the estimated historical DDCs to further enhance the precoder performance. Simulation results demonstrate that the proposed scheme facilitates a flexible reliability-latency tradeoff and achieves an excellent FER performance that approaches the lower bound obtained by a genie-aided benchmark requiring perfect ICSI at both the transmitter and receiver.

Two-Stage Constructions for the Rate-Compatible Shortened Polar Codes

In this paper, we propose the two-stage constructions for the rate-compatible shortened polar (RCSP) codes. For the Stage-I construction, the shortening pattern and the frozen bit are jointly designed to make the shortened bits be completely known by the decoder. Besides, a distance-greedy algorithm is presented to improve the minimum Hamming distance of the codes. To design the remaining Stage-II frozen bits, three different construction algorithms are further presented, called the Reed-Muller (RM) construction, the Gaussian Approximation (GA) construction, and the RM-GA construction. Then we give the row weight distribution numerical results of the generator matrix after the Stage-I and Stage-II constructions, which shows that the proposed constructions can efficiently increase the minimum Hamming distance. Simulation results show that the proposed RCSP codes have excellent frame error rate (FER) performances at different code lengths and code rates. More specifically, the RM-GA construction performs best and can achieve at most 0.8 dB gain compared to the Wang14 and the quasi-uniform puncturing (QUP) schemes. The RM construction is designed completely by the distance-constraint without channel evaluation thus has the simplest structure. Interestingly, it still has better FER performance than the existing shortening/puncturing schemes, especially at high signal noise ratio (SNR) region.

5G V2X Performance Comparison for Different Channel Coding Schemes and Propagation Models

Channel coding is a fundamental procedure in wireless telecommunication systems and has a strong impact on the data transmission quality. This effect becomes more important when the transmission must be characterised by low latency and low bit error rate, as in the case of vehicle-to-everything (V2X) services. Thus, V2X services must use powerful and efficient coding schemes. In this paper, we thoroughly examine the performance of the most important channel coding schemes in V2X services. More specifically, the impact of use of 4th-Generation Long-Term Evolution (4G-LTE) turbo codes, 5th-Generation New Radio (5G-NR) polar codes and low-density parity-check codes (LDPC) in V2X communication systems is researched. For this purpose, we employ stochastic propagation models that simulate the cases of line of sight (LOS), non-line of sight (NLOS) and line of sight with vehicle blockage (NLOSv) communication. Different communication scenarios are investigated in urban and highway environments using the 3rd-Generation Partnership Project (3GPP) parameters for the stochastic models. Based on these propagation models, we investigate the performance of the communication channels in terms of bit error rate (BER) and frame error rate (FER) performance for different levels of signal to noise ratio (SNR) for all the aforementioned coding schemes and three small V2X-compatible data frames. Our analysis shows that turbo-based coding schemes have superior BER and FER performance than 5G coding schemes for the vast majority of the considered simulation scenarios. This fact, combined with the low-complexity requirements of turbo schemes for small data frames, makes them more suitable for small-frame 5G V2X services.

A Simple Check Polytope Projection Penalized Algorithm for ADMM Decoding of LDPC Codes

ADMM penalized decoding method for Low-Density Parity-Check (LDPC) Codes can improve the frame error rate (FER) performance than the standard ADMM decoder by adding penalty terms to the objective function. However, penalty parameter optimization of the penalty terms is very difficult and extremely time-consuming. Additionally, the Euclidean projection onto the check polytope is the most complex part of ADMM-based decoding algorithms. In this paper, by dynamically choosing even-vertex in the check polytope closest to the input vector as the approximate projection, a simple and novel check polytope projection penalized algorithm for ADMM decoding is proposed which can avoid the tedious work of penalty parameter optimization and simplify the check polytope projection. The simulation results show that the proposed algorithm can substantially reduce the projection time while achieving better FER performance when compared with the existing penalized decoding. In particular, the proposed algorithm can save the decoding time by 23% to 41% compared with ADMM-PD-LSA algorithm.

LDPC Codes Over GF(q) With Alterable Subset for PAPR Reduction in OFDM Systems

Non-binary low-density parity-check (NB-LDPC) codes can exhibit more considerable coding gain than their binary counterparts in numerous cases. To further exploit the benefit of NB-LDPC codes, in this letter, a novel type of non-binary LDPC codes, alterable subset non-binary LDPC (AS-NB-LDPC) codes, is proposed for reducing the peak-to-average power ratio (PAPR) of orthogonal frequency division multiplexing (OFDM) systems. Firstly, we design the alteration scheme of AS-NB-LDPC codes to make <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$q$ </tex-math></inline-formula> -ary LDPC codes generate <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$q$ </tex-math></inline-formula> valid codewords through one alterable subset, and the codeword with the minimum PAPR is selected for transmission. Then inspired by the invertible subset for binary LDPC codes, the necessary and sufficient conditions for alterable subset generation are derived. Furthermore, we propose an improved progressive edge growth (PEG) construction method to obtain AS-NB-LDPC codes with favorable frame error rate (FER) performance. Simulation results verify the effectiveness of the proposed NB-LDPC codes.

Adaptive Gradient Descent Bit-Flipping Diversity Decoding

In this letter we propose a novel framework for designing decoders, for Low-Density Parity Check (LDPC) codes, that surpasses the frame error rate performance of Belief-Propagation (BP) decoding on binary symmetric channels. Its key component is the adaptation method, based on the genetic optimization algorithm, that is incorporated into the recently proposed Gradient Descent Bit-Flipping Decoding with Momentum (GDBF-w/M). We show that the resulting decoder outperforms all state-of-the-art probabilistic bit-flipping decoders and, additionally, it can be trained to perform beyond BP decoding, which is verified by numerical examples that include codes used in IEEE 802.3an and 5GNR standards. The proposed framework provides a systematic method for decoder optimization without requiring knowledge of trapping sets. Moreover, it is applicable to both regular and irregular LDPC codes.

Design of a Modified Interleaving Algorithm Based on Golden Section Theory Enhancing the Performance of Turbo Codes

This paper investigates the design of a modified matrix interleaving algorithm as a way to improve the performance of turbo codes. This proposed solution, known as the matrix-dithered golden (MDG) interleaver, utilizes the characteristics of a matrix interleaver combined with the golden section theory. The performance of the proposed interleaving method is compared with that of matrix (M), random (R), and dithered golden (DG) interleavers. The comparison is made in terms of bit error rate (BER), frame error rate (FER), computational complexity, and storage memory requirement. The turbo coded system is implemented and simulated using Matlab/Simulink software. Results of simulations performed both in the additive white Gaussian noise (AWGN) channel and the Rayleigh fading channel demonstrate the effectiveness of the proposed interleaver. The MDG interleaver is an effective replacement for random interleavers, as it improves BER and FER performance of the turbo code and is also capable of reducing the storage memory requirement without increasing the system’s complexity.

Performance analysis of LDPC coded GFDM systems

This paper analyzes the error probability performance of low-density parity-check (LDPC) coded generalized frequency division multiplexing (GFDM) systems over Rayleigh fading and additive white Gaussian noise (AWGN) channels. The initial log-likelihood ratio (LLR) expressions used in the sum-product algorithm (SPA) decoder are first derived for the system model presented in this paper. Based on the decoding threshold of the system, the frame error rate (FER) in the low E b / N 0 $E_b/N_0$ region is estimated by modeling the channel variations using the observed bit error rate (BER). Then, a lower bound based on the absorbing sets is proposed for FER when quantized SPA decoders are used. For AWGN channels, the lower bound can act as an estimate of the FER in the error-floor region if the absorbing set is dominant and its multiplicity is known. For Rayleigh channels, the lower bound can still be used to estimate the FER performance of selected codes. The estimation approach for the FER in the low E b / N 0 $E_b/N_0$ region and the lower bound on the FER in the high E b / N 0 $E_b/N_0$ region can be used as practical tools for evaluating different designs of GFDM-based systems in terms of the error probability performance. The quantization scheme has an important impact on the FER and BER performances. Randomly constructed and array-based LDPC codes are used to obtain numerical results that show the system performance and the accuracy of the proposed FER estimations.

Design and Analysis of NB QC-LDPC Codes Over Small Alphabets

We propose a novel approach to optimization of irregular nonbinary (NB) quasi-cyclic (QC)-LDPC codes over small alphabets. In this approach, first, the base parity-check matrices are constructed by a simulated annealing method, and then these matrices are labeled by the field elements while maximizing the so- called generalized girth of the Tanner graph. In order to analyze the performance of the constructed irregular NB LDPC codes, a new ensemble of irregular NB LDPC codes over the extensions of the binary Galois field is introduced. A finite-length random coding bound on the error probability of the maximum-likelihood (ML) decoding over the binary phase shift keying (BPSK) input AWGN channel for the new code ensemble is derived. The frame error rate (FER) performance of the sum-product belief-propagation (BP) decoding of the constructed NB QC-LDPC block codes is compared to that of both the optimized binary QC-LDPC block codes in the 5G standard and the best known NB QC-LDPC codes as well as to the derived random coding bound on the ML decoding error probability. It is shown that the obtained bound predicts the behavior of BP decoding performance of practical NB QC-LDPC codes more accurately than the BP decoding thresholds do.

Reconstruction-Computation-Quantization (RCQ): A Paradigm for Low Bit Width LDPC Decoding

This paper uses the reconstruction-computation-quantization (RCQ)paradigm to decode low-density parity-check (LDPC) codes. RCQ facilitates dynamic non-uniform quantization to achieve good frame error rate (FER) performance with very low message precision. For message-passing according to a flooding schedule, the RCQ parameters are designed by discrete density evolution. Simulation results on an IEEE 802.11 LDPC code show that for 4-bit messages, a flooding Min Sum RCQ decoder outperforms table-lookup approaches such as information bottleneck (IB) or Min-IB decoding, with significantly fewer parameters to be stored. Additionally, this paper introduces layer-specific RCQ, an extension of RCQ decoding for layered architectures. Layer-specific RCQ uses layer-specific message representations to achieve the best possible FER performance. For layer-specific RCQ, this paper proposes using layered discrete density evolution featuring hierarchical dynamic quantization (HDQ) to design parameters efficiently. Finally, this paper studies field-programmable gate array (FPGA) implementations of RCQ decoders. Simulation results for a (9472, 8192) quasi-cyclic (QC) LDPC code show that a layered Min Sum RCQ decoder with 3-bit messages achieves more than a 10% reduction in LUTs and routed nets and more than a 6% decrease in register usage while maintaining comparable decoding performance, compared to a 5-bit offset Min Sum decoder.

Node-Wise Scheduling Algorithm of ADMM Decoding Based on Line Segment Projection

In order to simplify the node-wise scheduling algorithm of the alternating direction method of multipliers (NS-ADMM) decoding, approximate line segment projection algorithm (LSA) is adopted to perform the projection in the node-wise scheduling algorithm. Experimental results show that using approximate line segment projection instead of precise projection in node-wise scheduling algorithm will yield a poor frame error rate (FER) performance. To solve this problem, dynamic scheduling strategy that selects the message-passing schedule according to the convergence status of the check node is proposed. Simulation results demonstrate that the modified node-wise scheduling algorithm based on line segment projection outperforms existing decoding algorithms in terms of FER performance and convergence speed, while it has good error correction performance with a lower computational complexity.

Low-Complexity Chase Decoding of Reed-Solomon Codes Using Channel Evaluation.

A novel time-varying channel adaptive low-complexity chase (LCC) algorithm with low redundancy is proposed, where only the necessary number of test vectors (TVs) are generated and key equations are calculated according to the channel evaluation to reduce the decoding complexity. The algorithm evaluates the error symbol numbers by counting the number of unreliable bits of the received code sequence and dynamically adjusts the decoding parameters, which can reduce a large number of redundant calculations in the decoding process. We provide a simplified multiplicity assignment (MA) scheme and its architecture. Moreover, a multi-functional block that can implement polynomial selection, Chien search and the Forney algorithm (PCF) is provided. On this basis, a high-efficiency LCC decoder with adaptive error-correcting capability is proposed. Compared with the state-of-the-art LCC (TV = 16) decoding, the number of TVs of our decoder was reduced by 50.4% without loss of the frame error rate (FER) performance. The hardware implementation results show that the proposed decoder achieved 81.6% reduced average latency and 150% increased throughput compared to the state-of-the-art LCC decoder.

Hardware Implementation of a Fixed-Point Decoder for Low-Density Lattice Codes

This paper describes a field-programmable gate array (FPGA) implementation of a fixed-point low-density lattice code (LDLC) decoder where the Gaussian mixture messages that are exchanged during the iterative decoding process are approximated to a single Gaussian. A detailed quantization study is first performed to find the minimum number of bits required for the fixed-point decoder to attain a frame error rate (FER) performance similar to floating-point. Then efficient numerical methods are devised to approximate the required non-linear functions. Finally, the paper presents a comparison of the performance of the different decoder architectures as well as a detailed analysis of the resource requirements and throughput trade-offs of the primary design blocks for the different architectures. A novel pipelined LDLC decoder architecture is proposed where resource re-utilization along with pipelining allows for a parallelism equivalent to 50 variable nodes on the target FPGA device. The pipelined architecture attains a throughput of 10.5 Msymbols/sec at a distance of 5 dB from capacity which is a 1.8times improvement in throughput compared to an implementation with 20 parallel variable nodes without pipelining. This implementation also achieves 24times improvement in throughput over a baseline serial decoder.

Rate‐compatible systematic polar codes

Puncturing and shortening are two common ways to achieve rate-compatible non-systematic polar codes (NSPCs). Systematic polar codes (SPCs) have been shown to outperform NSPCs with the same encoding and decoding complexity. However, rate-compatible SPCs have never been comprehensively studied in previous work. In this paper, two rate-compatible algorithms for SPCs are first proposed: uniform puncturing (UP) algorithm and uniform shortening (US) algorithm, which are referred to as SPC-UP and SPC-US, respectively. In order to effectively estimate the maximum likelihood decoding performance of punctured and shortened polar codes, subsequently, a distance spectrum calculation algorithm based on successive cancellation list (SCL) decoder for rate-compatible polar codes is proposed. Simulation results show that rate-compatible SPCs yield better bit error rate performance than rate-compatible NSPCs while they have the same frame error rate performance under different code rates and decoding algorithms. Eventually, union bounds that are obtained by the distance spectrum to provide the theoretical explanation for the superiority of rate-compatible SPCs are utilised.

Program error mitigation in MLC NAND flash memory with soft decision decoders

Benefiting from strong decoding capabilities, soft-decision decoding has been used to replace hard-decision decoding in various communication systems, and NAND flash memory systems are no exception. However, soft-decision decoding relies heavily on accurate soft information. Owing to the incremental step pulse programming (ISPP), program errors (PEs) in multi-level cell (MLC) NAND flash memory have different characteristics compared to other types of errors, which is very difficult to obtain such accurate soft information. Therefore, the characteristics of the log-likelihood ratio (LLR) of PEs are investigated first in this paper. Accordingly, a PE-aware statistical method is proposed to determine the usage of PE mitigation schemes. In order to reduce the PE estimating workload of the controller, an adaptive blind clipping (ABC) scheme is proposed subsequently to approximate the PEs contaminated LLR with different decoding trials. Finally, simulation results demonstrate that (1) the proposed PE-aware statistical method is effective in practice, and (2) ABC scheme is able to provide satisfactory bit error rate (BER) and frame error rate (FER) performance in a penalty of negligible increasing of decoding latency.

On Systematic Polarization-Adjusted Convolutional (PAC) Codes

Polarization-adjusted convolutional (PAC) codes were recently proposed and arouse the interest of the channel coding community because they were shown to approach theoretical bounds for the (128,64) code size. In this letter, we propose systematic PAC codes. Thanks to the systematic property, improvement in the bit-error rate of up to 0.2 dB is observed, while preserving the frame-error rate performance. Moreover, a genetic-algorithm-based construction method targeted to approach the theoretical bound is provided. It is then shown that using the proposed construction method systematic and non-systematic PAC codes can approach the theoretical bound even for higher code sizes such as (256,128).