Frame Error Rate Performance Research Articles

ADMM Check Node Penalized Decoders for LDPC Codes

Alternating direction method of multipliers (ADMM) is an efficient implementation of linear programming (LP) decoding for low-density parity-check (LDPC) codes. By adding penalty terms to the objective function of the LP decoding model, ADMM variable node (VN) penalized decoding can suppress the non-integral solutions and improve the frame error rate (FER) performance in the low signal-to-noise ratio (SNR) region. In this paper, we propose a novel ADMM check node (CN) penalized decoding algorithm. Codeword solutions which satisfy all parity-check equations will have smaller penalty values than non-codeword solutions, including the non-integral solutions. We discuss the required properties of CN-penalty functions, propose a few functions that satisfy those properties, and study their performance/complexity trade-offs. We also investigate the convergence properties of the proposed algorithm and prove that its performance is independent of the transmitted codeword. Using Monte Carlo simulations and instanton analysis, we then demonstrate that the proposed CN-penalized decoder outperforms ADMM VN penalized decoders in both waterfall and error floor regions. This comes at the expense of some increase in the decoding complexity.

A Robust and Low-Complexity Walsh-Hadamard Modulation for Doubly-Dispersive Channels

In this letter, we present a generic modulation framework for robust wireless communications over doubly dispersive channels. This robustness is achieved by spreading the symbols over time and frequency such that they experience the same channel gain. Interestingly, we show that our modulation framework is a generalization of the recently proposed orthogonal time frequency space modulation (OTFS). By exploiting an additional degree of freedom enabled by the generic framework, we propose in this letter a low-complex waveform based on the sparse Walsh-Hadamard transform (WHT). We show that the proposed sparse WHT modulation exhibits the same frame error rate performance as OTFS, while significantly reducing the implementation complexity due to the multiplication-free small-size WHT compared with the discrete Fourier transform used by symplectic finite Fourier transform (SFFT) of OTFS.

Simple Iterative Channel Coding and Modulation for Harbor Wireless Communications

Monitoring systems at the harbor require a simple communication technique to save battery energy, strong in error correction, and suitable to the harbor channel model, of which the channel is predicted to have more number of path. This paper proposes (i) a harbor channel model and (ii) a simple iterative repetition coding for harbor wireless communication of monitoring systems. The harbor channel model is derived using a series of computer simulations based on real-field harbor environmental parameters, while the proposed iterative channel coding is based on the repetition codes assisted by a doped accumulator (ACC) with a doping technique. Channel coding and doping rates are designed using an Extrinsic Information Transfer (EXIT) chart and are evaluated using a series of computer simulations in terms of Bit Error Rate (BER) and Frame Error Rate (FER) performances with an outage performance as the theoretical baseline for comparison. Since the EXIT curve of the repetition codes has steep curve, we use a non-Gray Quadrature Phase Shift Keying (QPSK) to achieve a better matching between the decoder and the demapper of harbor channels. We found that the proposed simple repetition codes and non-Gray demapper provide excellent performances for harbor communications with a cliff of BER curve. The results of this paper are expected to contribute to the development of a reliable wireless communications for the harbor monitoring applications.

Hardware Implementation for Belief Propagation Flip Decoding of Polar Codes

Belief propagation (BP) decoding has natural advantages in throughput for polar codes to meet high-speed and low-latency requirements. The soft outputs of BP decoding can be utilized further for joint detection and decoding in the baseband communication system. However, its error-correction performance is not comparable with the successive cancellation list (SCL) decoding. Belief propagation flip (BPF) decoding is recently proposed to improve the error-correction performance of BP decoding and indicates the potential to compete with SCL decoding. In this paper, we propose an advanced BPF (A-BPF) scheme that reduces the decoding latency with the help of one critical bit and improves the error-correction performance by the proposed joint detection criterion. To improve area efficiency in the hardware level, an optimized sorting network is proposed and applied for the A-BPF decoder. The decoder is implemented on 65 nm CMOS technology for length-1024 and rate-1/2 polar codes, and the results show that the proposed decoder can achieve a close frame error rate performance to the SCL decoder with four lists and deliver a throughput of 5.17 Gb/s at $E_{b}/N_{0}=4.0$ dB.

A Hybrid Check Polytope Projection Algorithm for ADMM Decoding of LDPC Codes

The Euclidean projection onto check polytope is the most complicated and time-consuming operation in the alternating direction method of multipliers (ADMM) decoding algorithm for low-density parity-check (LDPC) codes. Existing approximate even-vertex projection algorithm (EVA) can simplify the projection operation, but yields poor decoding performance. By alternately adopting EVA and other accurate projection algorithms, this letter proposes an innovative and simple hybrid projection algorithm (HPA) which can increase the percentage of unuseful projections. Simulation results show that the proposed algorithm can substantially reduce the projection time while achieving better frame error rate (FER) performance when compared with the standard ADMM decoding and the ADMM penalized decoding in the case of avoiding the tedious work of penalty parameter optimization. More importantly, compared with cut search algorithm (CSA), the proposed algorithm can significantly save the average projection time by nearly 80%, and the average decoding time by about 85%.

Hardware-Based Linear Program Decoding With the Alternating Direction Method of Multipliers

We present a hardware-based implementation of linear program (LP) decoding for binary linear codes. LP decoding frames error–correction as an optimization problem. In contrast, variants of belief propagation (BP) decoding frame error–correction as a problem of graphical inference. LP decoding has several advantages over BP-based methods, including convergence guarantees and better error-rate performance in high-reliability channels. The latter makes LP decoding attractive for optical transport and storage applications. However, LP decoding, when implemented with general solvers, does not scale to large blocklengths and is not suitable for a parallelized implementation in hardware. It has been recently shown that the alternating direction method of multipliers (ADMM) can be applied to decompose the LP decoding problem. The result is a message-passing algorithm with a structure very similar to BP. We present modifications to this algorithm, resulting in a more intuitive and hardware-compatible form. This is particularly true for projection onto the parity polytope: the major computational primitive for ADMM-LP decoding. Furthermore, we present results for a fixed-point Verilog implementation of ADMM-LP decoding. This implementation targets a field-programmable gate array (FPGA) platform to evaluate error-rate performance and estimate resource usage. We show that frame error rate performance well within 0.5 dB of double-precision implementations is possible with 10-bit messages. Finally, we outline research opportunities that should be explored en route to an application-specific integrated circuit (ASIC) implementation that is capable of Gigabit-per-second throughput.

A Fast Approximate Check Polytope Projection Algorithm for ADMM Decoding of LDPC Codes

Simplifying the Euclidean projection onto check polytope is an efficient way to reduce the computational complexity of alternating direction method of multipliers (ADMM) decoding algorithm for low-density parity-check (LDPC) codes. Existing algorithms for check polytope projection require sorting operation or iterative operation, which happens to be the most complex part of the projection. In this letter, a novel and fast projection algorithm is proposed without sorting and iterative operations. In the proposed algorithm, line segment projection replaces check polytope projection to approach approximate Euclidean projection at low computational complexity. Simulation results show that the proposed algorithm can substantially reduce the projection time while maintaining the frame error rate (FER) performance. In particular, the proposed algorithm can save the average projection time by 43% compared with cut search algorithm (CSA) when the dimension of the input vector is 20.

Adaptive 2-D Scheduling-Based Nonbinary Majority-Logic Decoding for NAND Flash Memory

This brief presents a nonbinary adaptive 2D scheduling-based majority logic decoding (NB-ATS-MLGD) algorithm for NAND flash memory. The proposed algorithms provide considerable tradeoff between error-correcting capability and decoding complexity, and make the NB-MLGD decoding more attractive for practical purposes in the multi-level cells (MLC) NAND flash memory. The most significant feature of the proposed NB-ATS-MLGD algorithm is the 2D layered scheduling strategy, where the decoding orders of check nodes (CNs) and variable nodes (VNs) are both adaptive. By leveraging on the MLC flash memory bit error patterns, an early-correcting (EC) criterion is incorporated into the NB-ATS-MLGD algorithm. Furthermore, the simplification and parallelization of proposed algorithms make them more practical in NAND flash memory. Simulation results show that the proposed algorithms increase the lifetime of MLC flash memory up to 3000 program-and-erase (PE) cycles and have desirable convergence speed compared with the conventional non-binary MLGD algorithm. When at low PE cycles, the NB-EC-ATS-MLGD algorithm improves frame error rate (FER) performance by more than 3 order of magnitudes compared with the conventional non-binary MLGD algorithm.

Pilot- and CP-Aided Channel Estimation in MIMO Non-Orthogonal Multi-Carriers

Motivated by 5G application requirements that challenge the use of orthogonal frequency division multiplexing (OFDM), non-orthogonal multi-carriers are being investigated. Unlike OFDM that takes advantage of orthogonal pilot observation, in non-orthogonal waveforms, pilots are contaminated by interference from multiple dimensions, i.e., inter-subsymbol-, inter-carrier-, and inter-antenna-interference, when multiple-input-multiple-output (MIMO) is also part of the transmission. Employing cyclic-prefix (CP) in multi-carrier systems not only protects the signal from inter-symbol-interference but also allows circular interpretations of the channel, which simplifies the estimation and equalization techniques. Nevertheless, the CP information is usually discarded at the receiver side. In this paper, by considering the fact that non-orthogonal waveforms suffer from multiple dimensions of interference, we derive a MIMO linear-minimum-mean-squared-error (LMMSE)-based parallel-interference-cancellation (PIC) method for joint channel estimation and equalization of non-orthogonal waveforms. Unlike the common practice, by properly localizing the pilots in time domain, we also use the pilots’ information from CP. We apply our proposed algorithm to a flexible non-orthogonal waveform known as generalized frequency division multiplexing (GFDM). Taking advantage of block-circularity of GFDM, we investigate the complexity aspects for such CP-aided LMMSE-PIC channel estimation. Through simulation results, we show that using CP information of pilots for GFDM gains up to 2.4-dB better frame error rate performance than an OFDM signal.

Physical‐layer information hiding technique for cognitive radio communications in cooperative relaying systems

This study presents a novel idea for information hiding at the physical layer level in order to securely transmit confidential cognitive radio data in cooperative relaying systems. Considering a cognitive radio network in which the secondary user cooperates with the primary system in relaying its data, in the proposed model, confidential cognitive information is hidden into the primary signal as a low-power noise at a symbol level such that it would be invisible by malicious users. The new hiding algorithm can be utilised along with any standard relaying scheme as long as the primary information signal is used as the cover data without significant degradation of the primary system performance. In the presence of cognitive data hiding, both the frame error rate and throughput performance of the primary and secondary systems are derived analytically for well-known relaying schemes such as fixed and incremental relaying protocols, when a selection-combining rule is utilised at the primary receiver for symbol detection. Using simulation results the correctness of the proposed theoretical analysis is verified. Moreover, using numerical results the existing tradeoff between the hiding cognitive capacity of the proposed model and the performance degradation of the primary system is highlighted.

A Mapping Shortening Algorithm for Polar Codes

Shortening is a common way to achieve rate-compatible polar codes. The existing shortening algorithms select shortened bits merely according to the structure of the generator matrix in order to make them known by the receiver. In this paper, we take into account the effect that the shortening has on the capacity of split channels and propose a shortening capacity mapping criterion. Based on the proposed mapping criterion, a mapping shortening (MS) algorithm is proposed. We theoretically prove that the MS algorithm can ensure that the proposed mapping criterion can be adopted reasonably and the shortened bits can be known by the receiver. In addition, the MS algorithm is proved to have the same order of complexity as existing shortening algorithms. What's more, we demonstrate the superiority of the MS algorithm over existing shortened algorithms from the perspective of channel capacity. Finally, the simulation results show that the MS algorithm has a significant advantage over existing shortening algorithms for the bit error rate (BER) and frame error rate (FER) performance under high code rates.

Hash-Polar Codes With Application to 5G

This paper presents a kind of concatenated polar codes called hash-polar codes with flexible outer code lengths, in which a hash function-based encoder is used as an outer encoder. A partial hash-polar code is also proposed to enhance the error-correcting performance at high signal-to-noise ratios. Since polar codes have been recommended by 3GPP as the channel coding scheme for the 5G enhanced mobile broadband control channel, the design of hash-polar codes for 5G is considered, where both good error-correcting performance and low false alarm rate (FAR) are required. The simulation results show that, under the 5G FAR requirement, the proposed hash-polar codes have similar frame error rate performance to cyclic redundancy check (CRC)-polar codes and perform better than parity check polar codes. In order to support early termination (ET) for 5G coding, we then propose segmented hash-polar codes, which exhibit the advantages of the ET gain compared with both CRC-polar codes and distributed CRC-polar codes.

Multi-CRC Polar Codes and M-SCFlip-Based Decoding

A multi-cyclic redundancy check (Multi-CRC) polar code construction algorithm is proposed in this paper to solve the error propagation problem of successive cancellation decoding for polar codes. In this algorithm, the information sequence is optimized into several segments to allow decoding errors to be corrected in time, minimizing the impact of error propagation. An improved multi-successive cancellation bit flipping (M-SCFlip) decoding algorithm is proposed to execute the bit flipping operation after CRC check-in each segment. In the low-SNR region, the proposed new multi-CRC polar code with successive cancellation list (SCL) decoding has a slight frame-error rate (FER) degradation compared with the original CRC polar code. With the M-SCFlip decoding algorithm developed in this paper, it achieves a better FER performance compared with the CRC polar code with successive cancellation (SC) and SCL ( $L\!=\!2$ ) decoding algorithms. In addition, it has a lower decoding delay and requires a lower memory space. For example, at a FER of 10−4 with the same code length and effective code rate, the proposed multi-CRC polar code with M-CFlip decoding achieves a 1.19 dB and 0.79 dB gains over existing CRC polar codes with the SC and SCL ( $L\!=\!2$ ) decoding algorithms, respectively.

Improvement of Fast Simplified Successive-Cancellation Decoder for Polar Codes

This paper presents a new latency reduction method for successive-cancellation (SC) decoding of polar codes that performs a frozen-bit checking on the rate-other (R-other) nodes of the Fast Simplified SC (Fast-SSC) pruning tree. The proposed method integrates the Fast-SSC algorithm and the Improved SSC method (frozen-bit checking of the R-other nodes). We apply a recognition-based method to search for as many constituent codes as possible in the decoding tree offline. During decoding, the current node can be decoded directly, if it is a special constituent code; otherwise, the frozen-bit check is executed. If the frozen-bit check condition is satisfied, the operation of the R-other node is the same as that of the rate-one node. In this paper, we prove that the frame error rate (FER) performance of the proposed algorithm is consistent with that of the original SC algorithm. Simulation results show that the proportion of R-other nodes that satisfy the frozen-bit check condition increases with the signal-to-noise-ratio (SNR). Importantly, our proposed method yields a significant reduction in latency compared to those given by existing latency reduction methods. The proposed method solves the problem of high latency for the Improved-SSC method at a high code rate and low SNR, simultaneously.

Exploiting variable-length padding bits for decoder performance improvement with its application to compressed video transmission

In many practical communications systems, the number of bits transmitted by each frame is fixed, whereas the number of information bits to be transmitted can be variable. One example is a typical communication system that consists of a source encoder followed by a channel encoder, where the former generates a variable-length information sequence per source data and the latter converts a fixed-length information sequence into a fixed-length codeword. Therefore, dummy bits are often padded (or stuffed) to the information bits prior to channel encoding at the transmitter so as to fill the gap, and they are usually discarded after channel decoding at the receiver. This paper proposes a novel use of such padding bits (PBs) for improving the performance of channel codes. We first observe that by considering the PBs embedded in the information part of systematic block codes as known bits and expurgating them at the receiver, it is possible to enhance the performance of the channel decoders, provided that the PBs are judiciously rearranged in the information sequence and they are perfectly known at the receiver. Nevertheless, the length of the PBs is random by nature, and transmitting such side information per frame would reduce the throughput. Therefore, we also develop a novel detector that can estimate the PB length reliably without the help of explicit side information. Through computer simulations employing an actual turbo code, the effectiveness of the proposed receiver with the PB length detector is demonstrated in terms of frame error rate (FER) performance. Furthermore, as a practical example of the proposed technique, its application to typical video transmission systems is addressed, where the performance improvement in terms of peak signal-to-noise ratio (PSNR) is observed.

Robust Modulation of PWM-Based Multi-Level Perpendicular Magnetic Recording for Conventional Media

In this letter, we propose a robust 3-ary modulation for a pulse width modulation (PWM)-based multi-level perpendicular magnetic recording. In the proposed 3-ary modulation, narrow-width pulses are restrained in PWM signal corresponding to resolution of magnetic media. We evaluate a user bit density (UBD) gain in our proposal using a low-density parity-check (LDPC) coded frame error rate performance. A low-resolution media is assumed as read/write (R/W) channel in the evaluation. Our simulation results show the proposed modulation has robust UBD gain compared with the conventional binary R/W systems in the low-resolution media. In addition, our proposed 7B6T modulation with non-binary LDPC codes over GF(128) has more than 6% density gain from the practical binary systems.

Rate-Compatible Tail-Biting Convolutional Codes for M2M Communications

We propose an algorithm to construct a group of rate-compatible tail-biting convolutional codes (RC-TBCCs) with consistently good frame error rate performance for both short and long information lengths. The algorithm considers the free distance property and the minimum distance profile of a TBCC jointly. We construct a group of RC-TBCCs with code rates $1/n$ , $3\leq n\leq 12$ . Numerical results show that the constructed RC-TBCCs have better frame error rate performance than the TBCCs used in LTE standards for various information lengths and code rates.

Novel polar-coded space-time transmit diversity scheme over Rician fading MIMO channels

In this paper, a polar-coded space-time transmit diversity (STTD) scheme is proposed in order to improve the performance of multiple-input multiple-output (MIMO) system. In Rician fading MIMO channels, the corresponding polar-coded STTD system can be equivalent to a single transmission channel for each polar code bit. Density evolutions for the polar-coded STTD systems are proposed based on the analyses of the single transmission channel. The proposed density evolutions provide preferable guidance to construct polar codes for the polar-coded STTD systems. Simulation results show that the BER performance of polar-coded STTD system is significantly improved as the number of antennas increases and the influence of the variable Rician K-factor of MIMO channels gradually vanishes. The proposed 2 × 2 polar-coded STTD system can provide better frame error rate (FER) performance than low-density parity-check (LDPC)-based system under low and mid code rates, and the average advantage is 0.3 dB approximately when the code rate is 0.25 and 0.2 dB when the code rate is 0.5.

MIMO Detector for LTE/LTE-A Uplink Receiver

We propose a carefully selected receiver structure, detector and detector implementation architecture for multiple-input multiple-output (MIMO) uplink base station receiver for fourth generation (4G) wireless cellular systems. First, we compare different receiver algorithms and structures for single-carrier frequency-division multiple access (SC-FDMA) uplink transmission to get a good understanding of the performance and complexity of these algorithms and their suitability for practical realization. One of those structures, namely the frequency domain MMSE equalization with sphere detection (SD), is proposed for implementation. The receiver consists of separate stages for inter-symbol interference (ISI) and inter-antenna interference (IAI) mitigation in frequency selective MIMO channels. Frame error rate (FER) performance is studied via simulations in realistic wireless channels and practical system parameters. K-best SD is selected as a detector algorithm for this receiver. There are several publications proposing a sort-free architecture for tree search type of detectors. Both a conventional K-best architecture and a sort-free architecture are implemented on a Xilinx Virtex-6 field-programmable gate array (FPGA) using High Level Synthesis (HLS) tool. Both architectures support 4 × 4 MIMO with 64-level modulation (64-QAM). Complexity results confirm that avoiding the sorter is not always recommended. The benefit of sort-free architecture depends on the system parameters.

Performance Analysis of CRC Codes for Systematic and Nonsystematic Polar Codes with List Decoding

Successive cancellation list (SCL) decoding of polar codes is an effective approach that can significantly outperform the original successive cancellation (SC) decoding, provided that proper cyclic redundancy‐check (CRC) codes are employed at the stage of candidate selection. Previous studies on CRC‐assisted polar codes mostly focus on improvement of the decoding algorithms as well as their implementation, and little attention has been paid to the CRC code structure itself. For the CRC‐concatenated polar codes with CRC code as their outer code, the use of longer CRC code leads to reduction of information rate, whereas the use of shorter CRC code may reduce the error detection probability, thus degrading the frame error rate (FER) performance. Therefore, CRC codes of proper length should be employed in order to optimize the FER performance for a given signal‐to‐noise ratio (SNR) per information bit. In this paper, we investigate the effect of CRC codes on the FER performance of polar codes with list decoding in terms of the CRC code length as well as its generator polynomials. Both the original nonsystematic and systematic polar codes are considered, and we also demonstrate that different behaviors of CRC codes should be observed depending on whether the inner polar code is systematic or not.