Fractional Divider Research Articles

A DDS-based PLL for 2.4-GHz frequency synthesis

In this transactions brief, we present a direct digital synthesizer (DDS)-based phase-locked loop (PLL), for frequency synthesis at 2.4 GHz with 80-MHz tuning range. The DDS signal is mixed with the voltage-control oscillator output in the PLL feedback path. This solution helps in avoiding some of the typical tradeoffs in PLL. In particular, it is possible to achieve a very high-frequency resolution together with fast settling and spectral purity. These characteristics are often incompatible both in integer and fractional dividers PLL. A prototype was fabricated on PCBs and tested. The settling time is about 3 /spl mu/s for 0.1 ppm (240 Hz) accuracy. Worst-case spurs are -53 dBc at 8-MHz offset from the carrier. The integrated phase noise in the band 1 kHz -1 MHz is 0.9/spl deg/ rms. This architecture is also suitable for direct frequency modulation, without necessitating any calibration system.

Effects of nonlinearities from the analog frequency-ramps of the fast network-analyser

Abstract. The developed network analyser with four ports allows very fast measurements of S-parameters in comparison with a conventional network analyser. This is possible because highly linear analogue frequency ramps are used. Thus the settling times of stepped frequency sweeps of conventional analysers are eliminated. The required high linearity and high stability of the frequency ramps is achieved by using fractional divider phase locked loop circuits. For a practical realization it is necessary to accept small nonlinearities for the linear analogue frequency ramps. For this reason investigations were performed to clarify effects of small nonlinearities on the measurement precision. Nonlinearities are willingly implemented by programming the fractional frequency ramps accordingly. The gained expertise allows for a further improvement of measurement accuracy and dynamic range.

A fully integrated 2.4-GHz LC-VCO frequency synthesizer with 3-ps jitter in 0.18-μm standard digital CMOS copper technology

In this paper, we present a fully integrated frequency synthesizer, using an LC voltage-controlled oscillator (LC-VCO) as the core oscillator. The synthesizer is designed to provide various output clock signals for a transceiver chip. Sampling clocks for on-chip analog-to-digital and digital-to-analog conversion modules are also generated, where low jitter is required. The synthesizer also includes an additional digital phase-locked loop and programmable fractional dividers. We present the general concept, special issues related to low jitter, and test chip results. The synthesizer achieves 3-ps rms long-term jitter on a 200-MHz output with 20-mW power and an area of 0.7 mm/sup 2/.

A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching

This paper describes a 1.8-GHz self-calibrated phase-locked loop (PLL) implemented in 0.35-/spl mu/m CMOS technology. The PLL operates as an edge-combining type fractional-N frequency synthesizer using multiphase clock signals from a ring-type voltage-controlled oscillator (VCO). A self-calibration circuit in the PLL continuously adjusts delay mismatches among delay cells in the ring oscillator, eliminating the fractional spur commonly found in an edge-combing fractional divider due to the delay mismatches. With the calibration loop, the fractional spurs caused by the delay mismatches are reduced to -55 dBc, and the corresponding maximum phase offsets between the multiphase signals is less than 0.20. The frequency synthesizer PLL operates from 1.7 to 1.9 GHz and the closed-loop phase noise is -105 dBc/Hz at 100-kHz offset from the carrier. The overall circuit consumes 20 mA from a 3.0-V power supply.

Measurement of the ramp linearity of extremely linear frequency ramps using a fractional dual loop structure

A dual loop synthesizer concept based on fractional divider techniques for measuring highly linear analog frequency ramps is presented. Due to the excellent sensitivity of the measurement set-up, relative nonlinearities as low as 10/sup -9/ are ascertainable. The measurements obtained with a prototype circuit are shown. They illustrate the expected high sensitivity. Furthermore, a vector network analyzer (VNA) based on this dual loop synthesizer is described which allows for very fast measurements.

Some Properties of Division Factor Sequences in Fractional Phase Locked Loops

Summary In the field of fractional divider phase-locked-loops (PLL) there exist several different methods for generating the division factor sequences controlling the programmable frequency divider in the PLL. The overall behaviour of the fractional PLL strongly depends on the proper choice of the division factor sequence. Therefore some concepts for generating these fractional sequences are discussed and the behaviour of the division factor sequences will be analysed with respect to the overall PLL behaviour. In addition some sources of disturbances are mentioned.

A highly linear frequency ramp generator based on a fractional divider phase-locked-loop

A highly linear analog frequency ramp generator based on a fractional divider concept is presented. The frequency ramp linearity achievable in this fractional phase-locked-loop configuration is better than 10/sup -4/. This value is revealed by numerical simulations as well as by measurements performed. With a prototype synthesizer implemented in a FMCW-radar system suitable for distance and velocity measurements.

Digital phase‐locked loops with a wide locking range using a fractional divider

AbstractDigital phase‐locked loops (DPLLs) are currently used widely in communications. However, conventionally used DPLLs have narrow locking ranges and long acquisition times. Although various types of DPLLs capable of overcoming these problems have been proposed, most of the DPLLs proposed have complicated circuit structures without significantly improved locking ranges. This paper proposes a new broadband DPLL with simple circuit configuration, a very wide locking range and fast acquisition time. to implement a wide locking range, the DPLL uses a fractional frequency divider that eliminates frequency error by changing the high‐speed clock according to the input frequency. After eliminating frequency error, the DPLL adjusts the phase of both the input and output signals by resetting the frequency divider in order to implement a fast acquisition time. This eliminates initial phase error. In addition, this system has a very simple configuration; only a fractional frequency divider is added to the simplest conventional binary quantized DPLL. the proposed DPLL is very practical because of its very wide initial locking range and the fact that the design of the DPLL does not depend on the system requirement as is the case with a conventional DPLL.

Digital Frequency Dividers

The paper comprehensively discusses the different up-to-date methods of pulse-frequency division with divider classification. It covers the design of odd and fractional integer divider with 50% out...