FR4 Channel Research Articles

A 15-Gb/s Single-Ended NRZ Receiver Using Self-Referenced Technique With 1-Tap Latched DFE for DRAM Interfaces

This brief presents a single-ended (SE) receiver (RX) with a self-referenced (SR) technique using sample and hold (S&H) circuits. The proposed RX does not require a reference voltage (VREF) for data recovery by comparing the present data with previous data. The RX was implemented as half-rate architecture to halve the clock frequency and facilitate the S&H operation. Moreover, the proposed decision feedback equalizer (DFE) is suitable for SR RX and improves the reliability of RX by eliminating inter-symbol interference (ISI). The prototype RX, fabricated using 28-nm CMOS technology, occupies a 0.0016 mm2 active area. The measurement result of the proposed RX achieves a bit-error-rate (BER) under 10−12 with a 15-Gb/s data rate in a 17-inch PCB FR4 channel. The RX consumes 13.56 mW of power and has a power efficiency of 0.90 pJ/bit.

A 5-Gb/s Adaptive Continuous Time Linear Equalizer Using Ferroelectric Capacitor

This article presents a 5-Gb/s continuous-time linear equalizer (CTLE) for serial link interface where adaptive nature is achieved using a ferroelectric capacitor. This barium strontium titanate (BST)-based STPTIC-15G2 capacitor model from STMicroelectronics provides a smooth 5:1 tuning range for a voltage range of 0&#x2013;18 V and eliminates the use of blocking capacitor required in case of varactor diode. The tunability of the high-pass filter response of the proposed CTLE provides the flexibility to meet the allocated loss budget of any serial link more precisely than a design with a discrete value capacitor. Also, its design methodology is much simpler than conventional MOSFET-based CTLE. Moreover, it avoids the use of complex algorithms seen in the case of digital equalization. For validation, the design is implemented on an FR4 board. While studying the data rate tolerance and channel tolerance of the printed prototype, the measured results closely match the simulation results. The compensation level of the equalizer is verified for an FR4 channel by varying its length from <inline-formula> <tex-math notation="LaTeX">$7^{\prime \prime }$ </tex-math></inline-formula> to <inline-formula> <tex-math notation="LaTeX">$28^{\prime \prime }$ </tex-math></inline-formula> which is equivalent to a change in insertion loss from 1.3 to 5.2 dB at 2.5 GHz, which is the Nyquist frequency for a 5-Gb/s signal. Also, for a <inline-formula> <tex-math notation="LaTeX">$28^{\prime \prime }$ </tex-math></inline-formula> FR4 channel, a channel loss requirement of 8&#x2013;9.5 dB is achievable by simply varying the applied bias to the ferroelectric capacitor from 0 to 10 V.

Current-integrating summer for DFE receiver with low common mode variation

This paper presents the design of current integrating based decision feedback equalizer (DFE) receiver. The proposed DFE incorporates a folded topology of current integrating summer which has reduced common mode voltage drop and variation at the summing nodes compared to existing topologies. The DFE uses a half-rate, soft decision architecture to alleviate the timing constraint of first feedback tap. Further, direct feedback architecture and reduced supply voltage are employed to reduce the power consumption. The DFE receiver has been implemented in 65 nm CMOS technology and operates at a data rate of 8 Gb/s over an 18.5 inch FR4 channel which has a loss of about 12.4 dB at 4 GHz frequency. It draws a current of 3.89 mA from a 0.9 V supply consuming a power of 3.5 mW.

A 5-bit 1.8 GS/s ADC-based receiver with two-tap low-overhead embedded DFE in 130-nm CMOS

Along with CMOS technology scaling, ADC-based serial link receivers have drawn growing interest in backplane communications but power dissipation of the ADC and complex digital equalizer in such digital receivers can be a limiting factor in high-speed applications. Implementing analog embedded equalization within the front-end ADC structure can potentially relax the ADC resolution requirement and reduces the complexity of the DSP which results in a more energy-efficient receiver. In this paper, the equivalence between the speculative comparisons of a loop-unrolling DFE and an ADC with non-uniform quantization levels is utilized to propose a novel ADC-based DFE receiver structure. The equivalency partially compensates for the power overhead imposed by loop-unrolling DFE. The 5-bit prototype receiver with two-tap embedded DFE is designed, laid out and simulated in a 130-nm CMOS process with 1.8 Gbps data rate. With embedded DFE disabled, the receiver achieves 4.57-bits ENOB and 1.77 pJ/conv.-step FOM. With 1.8-Gbps signaling across a 48-in FR4 channel, the two-tap DFE enabled receiver opens the completely closed eye and allows for a 0.26 UI timing margin at a BER of 10−9. The total active area is 0.21 mm2 and the ADC consumes 76 mW from a 1.2-V supply.

A Time-Based Receiver With 2-Tap Decision Feedback Equalizer for Single-Ended Mobile DRAM Interface

A time-based (TB) receiver (RX) with a 2-tap TB decision feedback equalizer (DFE) is proposed for mobile DRAM interface. The TB RX consists of a voltage-to-time converter (VTC), a TB DFE, and a time comparator. The VTC converts the RX input voltage to a time difference between two VTC outputs by using the difference in clock-to-Q delays between two latches with different input offset voltages. The TB DFE inserts an additional delay to one of the two VTC outputs and bypasses the other VTC output to increase the time opening. The time comparator makes a decision with the first arriving edge of the two outputs of the TB DFE. While the feedback loop delay must be less than 1 UI for proper operation in the conventional voltage-based DFE, the TB DFE allows the feedback loop delay up to 1.43 UI in this paper. A transmitter (TX) transmits a single-ended signal of 200-mV swing by using an n-over-n voltage-mode driver. The transceiver in a 65-nm CMOS process achieves a 12.5 Gb/s with a 0.8-V supply through a 15-inch FR-4 channel of 14-dB loss. The TX and RX chip consume 4.3 and 3.4 mA, respectively. The energy efficiency is 0.49 pJ/b.

Single‐ended 2 ch. × 3.4 Gbit/s dual‐mode near‐ground transmitter IO driver in 45 nm CMOS process

A smart dual-mode IO driver and termination scheme is proposed and power is efficiently consumed for both low-speed data transmission under 500 Mbit/s and high-speed data transmission up to 3.4 Gbit/s. During high speed data transmission, the driver uses near-ground signalling and pre-emphasis weight can be controlled for inter symbol interference (ISI) mitigation. The measured eye shows 17.8% vertically and 19.5% horizontally with finite impulse response (FIR) tap control for 15.75″ FR4 channel. The proto-type 2 channel single-ended driver has been implemented in 45 nm CMOS process and occupies 0.022 mm2 chip area.

A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface

A four-bit four-wire four-level (4B4W4L) single-ended parallel transceiver for the point-to-point DRAM interface achieved a peak reduction of $\sim 10$ dB in the electromagnetic interference (EMI) H-field power, compared to a conventional 4-bit parallel binary transceiver with the same output driver power of transmitter (TX) and the same input voltage margin of receiver (RX). A four-level balanced coding is used in this work to minimize the simultaneous switching noise at TX, to utilize a differential sensing without a reference voltage at RX, to maintain the pin efficiency of 100%, and also to reduce EMI by setting the sum of currents through the four wires to be zero. A capacitive pre-emphasis scheme modified for four-level signaling is also used at TX to compensate for inter-symbol interference. The transmitted four-level signals are recovered by six differential comparators with an offset compensation and a decoder at RX. The proposed transceiver chip fabricated in a 65 nm CMOS process consumes 2.39 pJ/bit with a 1.2 V supply and a 2 inch FR4 channel at 8 Gb/s.

Line-impedance matching and signal conditioning capabilities for high-speed feed-forward voltage-mode transmit drivers

This work presents the design and implementation of a power-efficient 2-tap feed-forward voltage mode driver which has impedance tuning and signal conditioning capabilities. The driver has a robust mechanism to match its impedance to the line impedance even when signal conditioning is enabled which minimizes reflection and improves signal quality. A mixed signal approach that detects and compensates for NMOS and PMOS transistor resistance variation is presented. An analog circuit detects the driver's resistance variation, and a digital circuit controls an analog compensation circuit to maintain line impedance matching for all signal conditioning configurations of the driver. When maximum signal conditioning is enabled, the driver can transmit a 40Gbits/sec PRBS7 signal through a 10 in. FR4 channel. It achieves a differential eye-opening amplitude of 100mVppd and an eye-opening width of 0.8UI consuming 9.7mW of at-speed power. Simulations demonstrate that worst case impedance deviation from 50Ω due to process, voltage and temperature variation is 2.7%. The driver is designed in 28nm CMOS process using a 0.85V nominal supply voltage. It is simulated using HSPICE circuit simulator and mixed mode simulations tools.

Adaptive Decision Feedback Equalizer with Hexagon EOM and Jitter Detection

This paper presents an adaptive decision feedback equalizer (DFE) utilizing a hexagon eye-opening monitor to detect both the violation of the minimum eye and the severity of the violation so as to allow different step sizes to be used in search for optimal DFE tap coefficients. In addition, a new slope detection method is used to detect the deviation of received data symbols from the desired one so as to guide the direction of search for the optimal DFE tap coefficients. The proposed adaptive DFE allows designers to freely set DFE constraints such as the minimum vertical eye opening, the minimum horizontal eye opening, and the maximum jitter of the sampling clock so as to address the needs of different applications. To validate its effectiveness, the proposed adaptive DFE is embedded in a 2 Gbps serial link designed in an IBM 130 nm 1.2 V CMOS technology. The link is analyzed using Spectre from Cadence Design Systems with BSIM4 device models. Simulation results demonstrate that the proposed adaptive DFE is capable of opening completely closed data eyes at the far end of a 2-m FR4 channel with 75 % vertical eye opening, 78 % horizontal eye opening, and 21 % data jitter while consuming 17.38 mW.

A 3x blind ADC-based CDR for a 20 dB loss channel

This paper proposes using a 3-bit ADC to blindly sample the received data from a channel with 20 dB loss at Nyquist at 3x the baud rate. By moving from 2x to 3x sampling, we reduce the required ADC resolution from 5-bit to 3-bit, thereby reducing the overall power consumption by a factor of 2. Measurements from our test chip fabricated in Fujitsu's 65 nm CMOS show a high frequency jitter tolerance of 0.25 UIpp for a 5 Gb/s PRBS31 with a 60 FR4 channel.

An Adaptive Equalizer for High-Speed Receiver using a CDR-Assisted All-Digital Jitter Measurement

An adaptive equalization scheme based on all-digital jitter measurement is proposed for a continuous time linear equalizer (CTLE) preceding a clock and data recovery (CDR) in a receiver circuit for high-speed serial interface. The optimum equalization coefficient of CTLE is determined during the initial training period based on the measured jitter. The proposed circuit finds automatically the optimum equalization coefficient for CTLE with 20”, 30”, 40” FR4 channel at the data rate of 5 Gbps. The chip area of the equalizer including the adaptive controller is 0.14 mm2 in a 0.13 μm process. The equalizer consumes 12 mW at 1.2 V supply during the normal operation. The adaptive equalizer has been applied to a USB3.0 receiver.

4×, 3‐level, blind ADC‐based receiver

The design of a 4× blind analogue-to-digital converter (ADC)-based receiver implemented in 65 nm CMOS technology is presented. The ADC, which has three levels with two adjustable thresholds, effectively implements a speculative decision-feedback equaliser. By reducing the ADC resolution and by simplifying the digital clock and data recovery design, the power consumption is reduced by a factor of 2 compared with previous works. Measurement results confirm a bit error rate of <10 − 12 at 5 Gbit/s with a high-frequency jitter tolerance of 0.39 and 0.31 UIpp for a 9.3 and a 12.9 dB FR4 channel, respectively. The entire receiver consumes 63 and 86 mW for the respective channels.

A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s

A differential transceiver achieves a 40 mVppd channel signal-swing, a 9 mVppd receiver (RX) input sensitivity, and a 0.59 pJ/b energy efficiency at 9 Gb/s with a 12 $^{\prime\prime}$ FR-4 channel. A current-integrating TIA (CI-TIA) is proposed as a RX pre-amplifier to enhance the RX input sensitivity by increasing the voltage gain of the CI-TIA to around 18 at 9 Gb/s. The RX circuit alone works up to 11 Gb/s with a 1 $^{\prime\prime}$ FR-4 channel. A voltage-mode pre-emphasis equalizer is combined with a current-mode logic (CML) driver at transmitter (TX) to save the low-frequency de-emphasis current of the conventional current-mode equalizer combined with a CML driver. The voltage-mode equalizer consists of a series connection of an inverter and a capacitor; the equalization coefficient is proportional to the supply voltage of the inverter. The transceiver chip in a 65 nm CMOS process consumes 2.8 mW at TX and 2.5 mW at RX with a 1 V supply and a 12 $^{\prime\prime}$ FR-4 channel at 9 Gb/s.

Minimum jitter‐based adaptive decision feedback equaliser for giga‐bit‐per‐second serial links

This study presents a minimum jitter-based adaptive decision feedback equaliser (DFE) for giga-bit-per-second (Gbps) serial links. The adaptation in search for the optimal tap coefficients of DFE is carried out with the objective to minimise data jitter at the edge of data eyes. Jitter minimisation is achieved by adjusting the slope of the DFE that counteracts that of the channel. The effectiveness of the proposed adaptive DFE is evaluated by embedding the DFE in a 2 Gbps serial link. The data link is analysed using Spectre from Cadence Design Systems with BSIM4 device models. Simulation results demonstrate that the proposed adaptive DFE is capable of opening closed data eyes with 83% vertical opening, 68% horizontal opening and 16% data jitter over 1 m FR4 channel while consuming 15.45 mW.

2‐tap pre‐emphasis SST transmitter with skin effect loss equalisation in 65 nm CMOS technology

A 2-tap pre-emphasis SST transmitter with skin effect loss equalisation is presented. The transmitter features the ability of compensating the low frequency loss caused by the channel skin effect. The transmitter equalisation coefficient setting and driver impedance adjustment are mutually decoupled. Fabricated in 65 nm CMOS technology, the transmitter can operate up to 20 Gbit/s while consuming 39 mW of power under a 1 V power supply. The skin effect loss equalisation is verified with a 24-inch FR4 channel under an 8 and 9 Gbit/s data rate.

A 6-b 1.6-GS/s ADC With Redundant Cycle One-Tap Embedded DFE in 90-nm CMOS

ADC-BASED serial link receivers are emerging in order to scale data rates over high attenuation channels. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-efficient receiver. This paper presents a 6-b 1.6-GS/s ADC with a novel embedded DFE structure. A redundant cycle technique is proposed for a time-interleaved SAR ADC, which relaxes the DFE feedback critical path delay with low power/area overhead. The 6-b prototype ADC with embedded one-tap DFE is fabricated in an LP 90-nm CMOS process and achieves 4.75-bits peak ENOB and 0.46 pJ/conv.-step FOM at a 1.6-GS/s sampling rate. Enabling the embedded DFE while operating at 1.6 Gb/s over a 46-in FR4 channel with 14-dB loss at Nyquist bandwidth opens a previously closed eye and allows for a 0.2 UI timing margin at a BER=10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-9</sup> . Total ADC power including front-end T/Hs and reference buffers is 20.1 mW, and the core time-interleaved ADC occupies 0.24 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area.

Differential Time Signaling Data-Link Architecture

A new time-based high-speed data-link architecture, which we call Differential time Signaling (DTS) is presented. A clock pulse is embedded in the transmitted signal and is used as a time reference against which the rising and falling data pulse edge timings are compared. Using the DTS approach, data encoding is achieved by spacing the time between the embedded clock edges and the data pulse edges using a hierarchical time-delay resolution assignment to each bit in the data sequence. The proposed link is shown to concentrate the signal energy in a low bandwidth while reducing clock jitter effect. A simulated 3 Gb/s 90 nm CMOS DTS link using a 500 MHz clock signal is also described to provide a flavor for a monolithic realization. As a proof of concept, 700 Mb/s and 1.6 Gb/s DTS-based links have been designed using a commercial FPGA board. The measured eye diagrams for the transmitted and received signals over a 40-inch FR4 channel are presented.

A 21-Gb/s 87-mW Transceiver With FFE/DFE/Analog Equalizer in 65-nm CMOS Technology

A 21-Gb/s backplane transceiver has been presented. The transmitter incorporates half-rate topology with purely digital blocks to substantially reduce power consumption. The receiver employs analog and decision-feedback equalizers in a full-rate structure to avoid complicated structure. The one-tap decision-feedback equalizer merges the summer and the slicer into the flipflop, shortening the feedback path and speeding up the operation considerably. Fabricated in 65-nm CMOS, the transceiver (excluding clock generating PLL and CDR circuits) delivers 21-Gb/s data (231- 1 PRBS) over 40-cm FR4 channel while consuming 87 mW from a 1.2-V supply.

Edge and Data Adaptive Equalization of Serial-Link Transceivers

Limited channel bandwidth introduces inter-symbol interference (ISI) at both data and edge samples. In addition to the ISI at data samples, ISI at the edge samples (edge ISI) increases the bit error rate (BER) by degrading on the eye diagram and increasing the jitter of the clock and data recovery (CDR). This work proposes a forward FIR equalizer and a decision-feedback equalizer (DFE) that compensate for both data and edge samples. To adapt both the data and edge equalizers, a modified LMS adaptation algorithm is introduced to achieve convergence. A transmitter and receiver are implemented in 0.13 mum and 0.18 mum technologies respectively. The edge ISI is improved by 20% and the jitter is improved by 10% in measurement. The link operates over a 120 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">''</sup> FR4 channel with 24 dB attenuation at Nyquist frequency, and the BER is below 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-14</sup> at 3.6 Gb/s.