FR4 Board Research Articles

Numerical Investigation on the Influence of Substrate Board Thermal Conductivity on Electronic Component Temperature Regulation

This study presents a detailed numerical analysis of substrate boards made from various materials (FR-4, Si cladding, and Cu cladding) with nine electronic components mounted on them. Each component is subjected to different heat fluxes, and the analysis covers both natural convection (NC) and forced convection (FC) modes of heat transfer at air velocities of 4m/s and 6m/s. The findings reveal that at an air velocity of 6m/s, using a copper cladding board significantly lowers the temperatures of the electronic components by 340C to 540C compared to FR-4 and Si cladding boards. Additionally, the copper cladding reduces the required air-cooling velocity by 2m/s and achieves a temperature reduction for the IC chips ranging from 3.500C to 13.120C. It is recommended to use an air velocity of 4m/s with copper cladding to minimize fan power consumption while maintaining component temperatures below 1250C. These results provide crucial insights for thermal design engineers, aiding in the selection of appropriate substrate boards for effective thermal management of electronic components. The study emphasizes the benefits of copper cladding in distributing heat more uniformly, reducing energy consumption, and maintaining optimal operating temperatures. Furthermore, it suggests that placing high heat-dissipating components at inlet or outlet points can minimize thermal interactions and overall configuration temperatures. The research offers valuable guidance to the heat transfer community, particularly electronic thermal designers, by highlighting the importance of substrate material choice and component placement in enhancing the reliability and lifespan of integrated circuits (ICs). The comprehensive analysis and recommendations serve as a vital resource for optimizing thermal control strategies in electronic devices, ultimately contributing to improved performance and durability.

Geometric modification and placement of high heat flux ic chips on substrates of different materials for enhanced heat transfer

This article presents the significance of using different sizes and positions of IC (Integrated Circuit) chips that are mounted on substrates of different materials. The ICs are cooled by forced convection in a horizontal wind tunnel. COMSOL Multiphysics 5.4 solve the IC chip cooling problem by selecting a conjugate heat transfer module with laminar flow. FR4, ba-kelite, single and multi-layer copper clad boards are used as substrate materials. Numerical simulations are performed for FR4, bakelite with a constant heat flux of 5000 W/m2, at 2.5 m/s air velocity. In contrast, single and multi-layer copper clad boards are studied for 10000 W/m2 with 1.5 m/s air velocity. The prime objective of this research is to use adequate size and placement of chips generating high heat fluxes for enhanced heat transfer. Results showed that larger chips placed at bottom rows and sequentially decreasing sizes in the subsequent rows for the same overall input for high substrate thermal conductivity give more heat dissipation. Among all configurations A0 – F considered in the study, case E provides minimum tempera-ture using single and multi-layer copper clad boards. In addition to modification of chip sizes, geometric spacing of X1/X2 = 1.8 results in lower maximum temperature.

Next Generation High Powered RF and Optical Packages

RF signals are radio waves that are very crucial for telecommunications. Quality communications require reliable materials which are appropriately processed to house high-powered semiconductors such as GaN and GaAs. It is equally crucial to accommodate passive electronic components along with these semiconductors into the housings for the Next Generation RF package or GenPack™. Evolving semiconductor technologies demand fail-safe packages to protect the devices in all applications and environmental conditions. Future aircraft, EV cars, spacecraft, augmented and/ or virtual reality headsets, medical devices and many more technologies require operating at a higher power and frequency with a proper thermal and power management platform. The higher speeds of telecommunications hinge on the performance of semiconductors and their packages. Therefore, the GenPack™ and packaging process are becoming crucial pieces of the supply chain. Rugged GenPack™ RF packages differ in several ways compared to the traditional air cavity packages. For instance, FR-4 or Flame-Retardant glass-reinforced epoxy laminate material can be replaced with Aluminum Nitride or Alumina Oxide, Silicon Nitride or even Sapphire. The switch offers mechanical bonding directly onto the thermal spreader. Traditional circuits created on printed circuit boards have limited ability to dissipate heat due to the low thermal conductivity of FR4. Circuits created on ceramic can dissipate higher amounts of heat. As in the organic FR4 boards, multiple vias can be formed in the ceramic substrates to create metal pads top the ceramic that are grounded to the flange beneath the ceramic. A metal flange can be positioned beneath the ceramic to provide a heat spreader and electrical ground that can be bolted onto a heatsink. Flanges can be made from a diamond metal matrix composite instead of lower thermal conductivity materials to provide much more efficient thermal transfer. Furthermore, narrow leads offer optimized impedance at RF and microwave frequencies. A range of ceramic and flange materials can be selected to optimize GenPack™ RF Packages with cost, quality, and performance in considerations for the respective applications.

Electronic gain study of single resistive electrode thick electron multiplier (RETGEM) radiation detectors with various resistive layers and substrates in P-10 gas

The study of resistive electrode thick gas electron multipliers (RETGEMs) of various designs is described. Four types of RETGEMs were tested. One was made of a substrate of a flame-retardant glass epoxy FR4 board coated with graphite as a resistive layer. The second was made of an FR4 board laminated with Kapton as a resistive layer. The third was made of a polyvinyl chloride (PVC) board coated with graphite as a resistive layer. Finally, a RETGEM with a diamond-like carbon coating produced by CERN was also tested. Multiple characteristics of the single RETGEM detector, such as absolute gas gains and maximum applicable voltages, were measured for all four types of RETGEMs at various voltages applied to the RETGEMs and various sizes of induction gaps, using Cm-244 alpha and F-55 X-ray sources. The results have shown that the highest absolute gas gain is achieved with the FR4 board laminated with Kapton. On the other hand, the PVC board coated with graphite gives the minimum voltage at which the signal can still be observed.

Effect of multiple discharges on accumulated damage to the DLC anode layer of a resistive Well Electron Multiplier

A prototype of the WEM (Well Electron Multiplier) detector with an active area of 10 × 10 mm2 and a resistive DLC anode was tested in terms of robustness to electrical discharges induced by highly ionizing particles (241Am alpha source). The perforated structure of the WEM detector was produced from a 500 μm thick FR4 with drilled holes of 200 μm in diameter and 500 μm in pitch. The resistive anode was made of 100 nm thick DLC layer with 30 MOhm/square sheet resistance deposited on the anode grid electrode. The anode grid electrode is used to distribute voltage to the resistive layer and provide fast charge evacuation. The detector was operated in Ar:CO2 (90:10) gas mixture at gas gain of 3,500. The alpha source was placed in the drift gap. The WEM detector with intrinsic capacitance of 34 pF did not show visible damage and changes in performance after 1 million accumulated discharges. To simulate a large area detector, we added a capacitance up to 1 nF in parallel with the test device. The results of the experiments with an additional capacitance revealed that a small WEM prototype can't be directly scaled to the dimensions more than 60 × 60 mm2 without losing the robustness to discharges. We assume that the observed damage could be caused by the design features of the prototype. The grid anode electrode with a thickness of 35 μm results in a gap between the perforated FR4 board and the resistive anode board. Simulations of the electric field distribution with Comsol Multiphysics software revealed a significant electric field strength in this gap. This could lead to electric discharge path bypassing the protective resistive DLC layer. A possible solution to this problem could be additional insulation of the anode grid electrode with a coverlay similar to that used in bulk MicroMegas production.

Fully integrated multi-level non-overlapping clock phase generator for pipelined ADCs in SiGe BiCMOS 0.13 μm

This work presents a novel multi voltage level non-overlapping clock phase generation architecture with a differential clock driver. It has a compact fully integrated power management, including LDOs and bandgap reference circuit. It is capable of controlling the PVT variation via SPI programming. It is functional from 50 MHz up to 1 GHz, to be used for pipelined ADCs. The core chip achieves SNRjitter around 72 dB from 50 MHz to 150 MHz, and above 68 dB from 150 MHz to 400 MHz, above 60 dB up to 1 GHz clock signals. The core section consumes 19 mA at 1 GHz from an external supply of 3 V. The chip occupies 1235 μm × 1300 μm, in a SiGe BiCMOS 0.13 μm process. The clock generation system occupies 400 μm × 360 μm silicon area, excluding I/O pads and interface circuits. It is packed in a 5 mm × 5 mm QFN32 package and assembled onto an FR4 board.

A Novel Tuning Fork-Shaped Tri-Band Planar Antenna for Wireless Applications

A novel tuning fork-shaped tri-band planar antenna (NTTPA) for the LTE 2.3/3.8-GHz band, WLAN 2.4/5.2/5.8-GHz band, and WiMax 2.5/3.5/5.5-GHz band is presented in this letter. By introducing an asymmetrical turning fork-shaped patch and an inverted L-shaped patch, three notched bands can be generated to form a triple-band operation. The antenna is fabricated on an FR4 board and excited by an SMA connector using a microstrip line. The antenna structure is simple and has a compact size of 45 mm × 40 mm. The measured operating frequency covers 2.2–2.63, 2.73–3.8, and 5.13–6.3 GHz, and the percentage bandwidth is close to 53.3% (S11 < −9.8 dB from 2.2 to 3.8 GHz) and 20.5% (S11 < −10 dB from 5.13 to 6.3 GHz). The calculated and experimental results suggest that the proposed antenna is one of the best candidates for wireless communication systems in terms of multi operating bands, broad percentage bandwidth (BW), compactness, stable radiation pattern, easy processing, and low cost.

A compact and cost effective quasi-in-situ method to characterize broadband RF shielding effectiveness of materials for advanced microelectronic packaging

At present, one of the major measures to suppress electromagnetic (EM) radiation inside advanced integrated microelectronic packages is the proper placement of electromagnetic shielding. Existing shielding effectiveness (SE) characterization technologies are always intended for enclosure evaluation, which are costly and time consuming, demanding complicated test instrument configuration, fixture setup, and a large room to accommodate the whole test system, especially when broadband test is required in which a series of narrowband antennas are to be switched during the test; additionally, the way test samples are assembled is quite different from that in the final package application. Therefore, their practical value and adaptation in SE evaluation are limited in the view of the professionals engaged in micro/nano electronics package research, development, manufacturing and application, and indeed there exist urgent desires for a compact and cost-effective technology characterizing in-situ the broadband effectiveness of shielding materials for EM radiation suppression in high-density heterogeneously integrated packages and relevant miniaturized system integration scenarios. Accordingly, in this paper a compact dual-port microstrip antenna test fixture working in pairs is designed and prototyped, which provides a quasi in-situ environment for the test sample, and only a vector network analyzer (VNA) is needed which just measures the fixture port scattering parameters so as to conveniently and faithfully reveal the SE. Solid modeling and full-wave simulation for the broadband return loss, insertion loss and radiation pattern of the test setup are carried out by a high-frequency electromagnetic structural analysis software for design verification. The actual test is carried out by loading heat insulation board, heat insulation board laminated with aluminum foil, PureBlue board and FR4 board samples. By comparing the SE of different materials, the validity for the proposed microstrip antenna test fixture in characterization is confirmed.

Computational cooling performance of electronic chips on printed circuit boards

Effect of cooling performance of heated modules resembling integrated circuit (IC) chips on printed circuit boards (PCBs) under natural and forced convection is investigated. Commercially available four different types of substrate materials viz. silica glass, glass epoxy FR4, bakelite, and copper-clad board (CCB) is used for the simulation study. Natural and forced convection cooling scenarios are used for thermal performance with a power input of 7.5 W and 15 W for heaters equipped on a substrate. The main motive of this work is to present and compare thermal performance of heated modules on different substrate materials. Results of FR4 and bakelite with a power input of 7.5 under natural convection are compared with forced convection results at Re = 500 for the same power input. The results show that copper clad boards give a better cooling performance in natural convection scenarios for both the power inputs of 7.5 W and 15 W.

Improving the reliability of power LEDs with diamond boards

Despite being efficient devices, when compared to other light sources, high power light emitting diodes (LEDs) suffer from heating effects that have a negative impact on their reliability. Power LEDs are typically assembled on metal core printed circuit boards (MCPCBs) to facilitate the extraction of the heat. Diamond boards can also be used for the same purpose, since diamond is the best isotropic conductor of heat known to man and simultaneously an electrical insulator. In order to evaluate the impact of the boards on the device lifetime, high power Cree LEDs were mounted on FR4, MCPCB, and diamond boards. The case temperature was measured for different current ratings, and the aging acceleration factor of the devices mounted on FR4 and diamond boards was estimated relatively to the LEDs mounted on the MCPCB boards. Diamond boards were shown to have a tremendous impact on the lifetime; for the nominal current level, and depending on the activation energy of the aging processes, the LEDs mounted on diamond boards age 60–80 % slower than their counterparts mounted on the MCPCB boards.

A 5-Gb/s Adaptive Continuous Time Linear Equalizer Using Ferroelectric Capacitor

This article presents a 5-Gb/s continuous-time linear equalizer (CTLE) for serial link interface where adaptive nature is achieved using a ferroelectric capacitor. This barium strontium titanate (BST)-based STPTIC-15G2 capacitor model from STMicroelectronics provides a smooth 5:1 tuning range for a voltage range of 0&#x2013;18 V and eliminates the use of blocking capacitor required in case of varactor diode. The tunability of the high-pass filter response of the proposed CTLE provides the flexibility to meet the allocated loss budget of any serial link more precisely than a design with a discrete value capacitor. Also, its design methodology is much simpler than conventional MOSFET-based CTLE. Moreover, it avoids the use of complex algorithms seen in the case of digital equalization. For validation, the design is implemented on an FR4 board. While studying the data rate tolerance and channel tolerance of the printed prototype, the measured results closely match the simulation results. The compensation level of the equalizer is verified for an FR4 channel by varying its length from <inline-formula> <tex-math notation="LaTeX">$7^{\prime \prime }$ </tex-math></inline-formula> to <inline-formula> <tex-math notation="LaTeX">$28^{\prime \prime }$ </tex-math></inline-formula> which is equivalent to a change in insertion loss from 1.3 to 5.2 dB at 2.5 GHz, which is the Nyquist frequency for a 5-Gb/s signal. Also, for a <inline-formula> <tex-math notation="LaTeX">$28^{\prime \prime }$ </tex-math></inline-formula> FR4 channel, a channel loss requirement of 8&#x2013;9.5 dB is achievable by simply varying the applied bias to the ferroelectric capacitor from 0 to 10 V.

Triangle Shaped Antenna Design for IoT-based Lorawan Applications

The antenna has a massive potential in the world of the Internet of Things (IoT). However, the miniaturized antenna design is a massive task as lorawan applications consume relatively lesser power. The design in this paper is a miniaturized E-shaped patch antenna for LoRa devices. The patch’s physical dimensions for the proposed antenna are 160mm*170mm*1.6mm on the FR-4 board. The simulated results were found satisfactory and can operate over the 868 MHz frequency band.

Effect of thermal conductivity of substrate board for temperature control of electronic components: A numerical study

The current study deals with the numerical investigation of the substrate board characteristics using different materials (FR4, silicon cladding and copper cladding) on which nine nonidentical electronic components (ECs) are mounted, which are supplied with nonuniform heat flux. The study is conducted for natural and forced convection (3[Formula: see text]m/s and 5[Formula: see text]m/s) modes of heat transfer. It is observed that for 5[Formula: see text]m/s the temperature of the ECs is dropped by 30–47∘C using copper cladding board in comparison to FR4 and silicon cladding board. It is also noted that with the use of copper cladding board the velocity of air required for cooling the ECs is substantially reduced by 2[Formula: see text]m/s and the temperature of the IC chip is reduced by 1.50–11.12∘C.

A thin and low-cost scalable waveguide load absorber

In this paper, a set of simple S-band waveguide absorbers are designed and implemented on a low-cost FR4 substrate. This is to provide an alternative for conventional waveguide absorbers, which are generally bulky and costly. The proposed structure is composed of only two open-ended resonator strips on a low-cost, 3.2-mm thick FR4 board. These absorbers operate with the same fundamentals as absorbers based on the frequency selective surfaces. The proposed innovative waveguide absorber load is mode-independent and designed without any connection between the strips and the waveguide. Simulations and measurements indicated an approximately 2.2% of bandwidth, with a 99% absorption rate at the center frequency. A complete parameter study is also performed to show the robustness of the design, besides enabling tuning for use in other microwave waveguides. A good agreement between simulated and measured results confirms the functionality of the absorber.

Utilizing a High-Speed Marx Supply Modulator in an Amplitude-Modulated Mixerless Transmitter for 64 QAM

This article reports on the theory and application of a high-speed Marx generator (HSMG) circuit to realize supply modulation (SM). In order to achieve high-modulation bandwidth, the supply modulator complexity is kept low, enabling multilevel SM with four discrete voltage levels. A prototype is designed and fabricated on a four-layer FR4 board. The efficiency of the proposed modulator is measured with passive loads, achieving 89% at the 5-MHz switching frequency. Applied to a power amplifier (PA), the modulator demonstrates an error vector magnitude (EVM) of 2.64% at 10-MHz switching frequency with a four-ASK signal. Finally, the HSMG is utilized in an innovative mixerless transmitter architecture. Its capabilities are validated at the center frequency of 3.5 GHz for different modulation bandwidths from 2 up to 70 MHz and different constellation schemes-16 QAM, 32 QAM, and 64 QAM. EVM of 5.88% at 10-MHz bandwidth with 64 QAM is obtained without digital predistortion (DPD).

Multiple element of miniaturized printed log-periodic second series koch dipole array antenna for wideband chipless RFID tag reader

This paper aims to produce a low profile, wideband, and high gain antenna for chipless RFID tag readers. A miniaturized and wideband printed Log-Periodic Second Series Koch Dipole Array (LPSSKDA) with eleven elements operating over 0.8 GHz-3.2 GHz is designed using the FR4 board. The single LPSSKDA antenna, which acts as the chipless RFID reader antenna having gain between 5.2 and 6.1 dBi and frequency range from 1-3 GHz. A double element of the LPSSKDA antenna is proposed for improving the antenna gain to 6.9-7.9 dBi over the frequency range. The antenna is fabricated to validate the simulation and measurement results in terms of reflection coefficient, radiation pattern, and surface current distribution.

Design of a multimode tunable low noise amplifier for software defined radios

This Letter presents the design and analysis of a tunable low noise amplifier (LNA) capable of achieving single band, dual band and wideband operations. The circuit features a modified tunable open stub matching to achieve a reconfigurable multiband response. The LNA adopts a varactor diode in the input matching stage to achieve reconfigurable modes. Two bias conditions for the varactor diode are analysed. The forward bias condition yields a wideband mode (1.6 to 2.5 GHz) and zero bias results in a concurrent dual band mode (0.9 and 1.7–2.5 GHz). In reverse bias condition, the bias voltage of varactor diode () can be tuned to achieve one single band mode (1 GHz), and a tunable concurrent dual band mode, where the first band is fixed at 1 GHz and the second band is continuously tunable from 1.7 to 2.5 GHz. The LNA is fabricated in microwave integrated circuit process on an FR-4 board. The measured power gain is 7–15 dB and noise figure is 1.2–2.2 dB across all bands. The measured 1 dB compression () is , and at 0.9, 1 and 2.4 GHz, respectively.

A Lightweight Planar Ultrawideband UHF Monopole Mills Cross Array for Ice Sounding

An electrically large ultrawideband ultrahigh frequency (UHF) monopole antenna array has been designed to sound up to 3 km of ice and meet the logistical requirements of transportation to arctic regions. The monopole array is comprised of 16 planar subarray modules, which in combination form a 16 m by 17 m Mills cross array configuration to maximize sensitivity and spatial selectivity in both cross-track and along-track directions. Each planar subarray module is 1 m by 2 m in size with a 6.35 cm thick rigid insulation foam panel separating the individual monopole elements from metal foil ground plane on the top such that the maximum radiation is directed to nadir. Each subarray panel consists of 4 by 8 circular monopole antenna elements with a spacing of 0.25 m. Each monopole element is printed on a 130 mm by 80 mm 62 mil FR4 board. The total weight of each subarray panel is 9 kg, making for very lightweight and low-profile antenna construction. The antenna array together with the radar system was deployed to the East Greenland Ice-coring Project site in August 2018 for demonstrating surface-based ice sounding at the UHF band.

Mimo Antenna for LTE Advance Application

In this paper, the MIMO antenna design for LTE Advance Application is realized. The paper focused on designing high gain MIMO antenna for LTE Advance Application. The purpose of designing a MIMO antenna is to fix the problem of low/moderate gain of SISO antenna since to have higher gain in LTE Advance normally is by having array antenna which lead to larger antenna and higher cost and mutual coupling between MIMO before can cause loss of spectral efficiency and degrade performance of a MIMO system. The designed antenna used FR-4 board as the substrate material due to its good parameters for most application. It is also more available and much cheaper than any other PCB material. Meanwhile, copper has been chosen as conductive material which copper is high relative and also cheap. For the designing stage, Advance Design System (ADS) software has been used to design the antenna. The ADS software also has been used for the simulation of the designed antenna in terms of return loss (S11) and (S22), mutual coupling (S12) and (S21), gain, directivity, radiation pattern, power radiated and also impedance matching. For the measurement stage, the fabricated antenna has been using by Vector Network Analyzer (VNA). From this project, it can be seen that the measurement results were slightly different from the simulation results due to a few factors such as cable losses, and also soldering technique. However, the designed antenna still met the requirement of efficiency which is less than -10 dB of return loss and get at a frequency of 2.5 GHz.

Design of an Elliptical Patch Antenna for RF Energy Harvesting Application in 2.4 GHz Frequency band

In this paper, the design and prototype of an elliptical patch antenna is presented, which operates at the frequency of 2.4 GHz frequency band. It harvests energy from ‘Radio Frequency’ waves. The elliptical antenna has an antenna substrate made with FR4 board with dielectric constant of 3.95. The paper presents the simulation results of the basic parameters of the antenna such as: return loss, input impedance, bandwidth, gain, directivity and efficiency. The experimental results for return loss, band width and input impedance was also presented in the paper. The antenna has a gain of 5.84 dB, directivity of 6.25 dBi, return loss of -43.35 dB, bandwidth of 373 MHz, input impedance of 50.35 Ω and efficiency of 90%. The high gain, properly matched impedance for minimum return loss and high efficiency of the antenna make it eligible for energy harvesting application.