FPGA Space Research Articles

High randomness hyperchaos-based parameterizable TRNG: Design, FPGA implementation and exhaustive security analysis

Recently, chaotic systems have become a thrilling discipline for information security applications, particularly in designing entropy sources. This paper presents a novel technique to tame an optimized 4D hyperchaotic Lorenz system by building a reconfigurable high randomness and low-cost hardware true random number generator (HC-HTRNG). Moreover, the proposed architecture has been modeled using the fourth-order Runge–Kutta method (RK4) and the 32 bits (10Q22) fixed-point arithmetic representation. The adopted methodology consists of two crucial points. First, we proposed using both intermediate and final solutions of the RK4 method as a raw data source for our HTRNG. The provided raw data are used to generate random numbers with parameterizable sizes. This approach reduces the design latency from four clock cycles to only one cycle while increasing the generation speed and the entropy value. Second, the designed HC-HTRNG integrates a FIPS 140-2-based built-in self-security test module (BISSTM). The BISSTM is used as an environment failure protection and testing mechanism (EFPTM) to guarantee online and continuous control of the proposed HC-HTRNG’s reliability and availability. Furthermore, the proposed HC-HTRNG has been implemented on the Xilinx ML605 FPGA platform using an RTL design based on the VHDL description of the RK4 method. A panoply of online/offline investigations and experiments were carried out intensely, deeply, and thoroughly to analyze, evaluate and validate the robustness and security aspects of the proposed HTRNG regarding all the aspects related to embedded system security. Notably, the evaluations were conducted regarding of chaos validation, security analysis, statistical tests, design performances, and comparisons. The investigations and implementation findings validate that the proposed architecture can attain high performance in terms of maximum post place and route operating frequency (MPRF) and throughput while occupying low FPGA space. Furthermore, timing and power efficiencies result presents an excellent trade-off between design efficiency and high-performance achievement. To the best of our knowledge, the proposed HC-HTRNG is the only one in the literature whose investigation has been subjected to 25 analyses, including 17 related to security aspects. Moreover, among all TRNGs, our generator is the only one that successfully passed seven statistical test suites, as well as the hardest and the most complex.

The History, Status, and Future of FPGAs

This article is a summary of a three-hour discussion at Stanford University in September 2019 among the authors. It has been written with combined experiences at and with organizations such as Zilog, Altera, Xilinx, Achronix, Intel, IBM, Stanford, MIT, Berkeley, University of Wisconsin, the Technion, Fairchild, Bell Labs, Bigstream, Google, DIGITAL (DEC), SUN, Nokia, SRI, Hitachi, Silicom, Maxeler Technologies, VMware, Xerox PARC, Cisco, and many others. These organizations are not responsible for the content, but may have inspired the authors in some ways, to arrive at the colorful ride through FPGA space described above.

Formalization of the concept of adaptive tasks mapping in the reconfigurable computers on FPGA

The effectiveness of data processing in the reconfigurable computer systems depends significantly on the unproductive time costs of the reconfiguration of the FPGA computational space. It is an important modern problem that hinders the intensive progress of reconfigurable computations. The aim of the research is to improve the efficiency of the process of tasks mapping into the reconfigurable computing structure of the dynamically RCs by reducing the communication delays when the reconfiguring FPGA space in the Run Time mode. Mathematical models for determining the main efficiency criteria of the dynamically RCs and estimating the execution time of the main stages of adaptive tasks mapping that take into consideration the influence of delays of the configuration data transfer at all organization levels of the system are proposed. The concept of adaptive tasks mapping into the dynamically reconfigurable FPGA space based on the new approach to the transformation of algorithms’ MDG and the multilevel configuration data caching is proposed and formalized. That allows the realization of various strategies of adaptive tasks mapping based on the criteria of overhead time minimization considering FPGA hardware limitations and parameters of the changing computing environment during the tasks mapping. The experiments showed that the use of adaptive tasks mapping allows to reduce the overhead time and increase the effectiveness of reconfigurable computations for executing the algorithms with frequent repetition of similar tasks.

Multicore reconfiguration platform an alternative to RAMPSoC

The current state of the art in processor performance improvement is multicore-processor systems. These systems offer a number of homogeneous and static processor cores for the parallel distribution of computational tasks. A novel idea in this research field is introduced by the Runtime Adaptive Multi-Processor System-on- Chip (RAMPSoC) approach. It uses a dynamic and partial reconfigurable system to offer a heterogeneous multicore-processor system. It is runtime adaptable to applications needs and provides a high degree of freedom for system design and task distribution. The continuation of this idea is the Multicore Reconfiguration Platform (MRP) presented in this paper. Its fine grained reconfiguration framework offers a higher degree of freedom and achieves a better FPGA space exploitation, reduced power consumption and a more precise adaption to application requirements.

ROUTING AWARE PLACEMENT ALGORITHM AND EFFICIENT FREE SPACE MANAGEMENT FOR RECONFIGURABLE SYSTEMS

In partially reconfigurable devices like FPGA, logic resources and communication channels can be reconfigured without affecting other section of the device. This allows parallel execution of multiple tasks on a FPGA. Due to limited resources on a FPGA, an effective management for efficient execution of tasks is required. We present a new approach for management of FPGA logic resources and also communication channels in an online task placement. The approach creates communication channels between the tasks and also tasks with I/O elements without requiring extra computation overhead. We present a fast algorithm for searching MERs for management of FPGA space. Then, we present a exact routing algorithm to find distance and create exact path between two set of tasks. A new fitting strategy based on the rate of communication between the tasks is also presented. The results indicate the proposed strategy and also its combination with some other known strategies can improve the quality of placement.