FPGA Simulation Research Articles

ExaFlexHH: an exascale-ready, flexible multi-FPGA library for biologically plausible brain simulations.

In-silico simulations are a powerful tool in modern neuroscience for enhancing our understanding of complex brain systems at various physiological levels. To model biologically realistic and detailed systems, an ideal simulation platform must possess: (1) high performance and performance scalability, (2) flexibility, and (3) ease of use for non-technical users. However, most existing platforms and libraries do not meet all three criteria, particularly for complex models such as the Hodgkin-Huxley (HH) model or for complex neuron-connectivity modeling such as gap junctions. This work introduces ExaFlexHH, an exascale-ready, flexible library for simulating HH models on multi-FPGA platforms. Utilizing FPGA-based Data-Flow Engines (DFEs) and the dataflow programming paradigm, ExaFlexHH addresses all three requirements. The library is also parameterizable and compliant with NeuroML, a prominent brain-description language in computational neuroscience. We demonstrate the performance scalability of the platform by implementing a highly demanding extended-Hodgkin-Huxley (eHH) model of the Inferior Olive using ExaFlexHH. Model simulation results show linear scalability for unconnected networks and near-linear scalability for networks with complex synaptic plasticity, with a 1.99 × performance increase using two FPGAs compared to a single FPGA simulation, and 7.96 × when using eight FPGAs in a scalable ring topology. Notably, our results also reveal consistent performance efficiency in GFLOPS per watt, further facilitating exascale-ready computing speeds and pushing the boundaries of future brain-simulation platforms. The ExaFlexHH library shows superior resource efficiency, quantified in FLOPS per hardware resources, benchmarked against other competitive FPGA-based brain simulation implementations.

Real-Time Digital Mapped Method for Sensorless Multitimescale Operation Condition Monitoring of Power Electronics Systems

Operation condition monitoring of power electronics systems can improve analysis visibility for device administrators and researchers. However, the current sensor-based monitoring methods have limitations in accurately monitoring variables at multi-timescales. This article presents a real-time digital mapped (RTDM) method for the sensorless multi-timescale operation condition monitoring in power electronics systems using FPGA simulators. The mathematic models of power converters are deployed in the simulator considering multi-timescale characteristics. Both the digital simulator and the physical power converter are controlled by the same control signals, allowing the simulator to map the accurate operation conditions of the power converters without additional physical sensors. The RTDM method can monitor variables on the switching period timescale to the system transient timescale due to the consideration for the ideal switch modeling of the semiconductor switch. The effectiveness of the proposed method is demonstrated using a 30kW DAB converter as an example, through the integration of an experimental prototype and a simulator to create an RTDM platform. This method offers an easy and sensorless way to monitor multi-timescale variables in power electronics systems, providing a more comprehensive and visual analysis of their operation.

Accelerating inverter control system testing and verification based on FPGA

Traditional FPGA development faces challenges such as long development cycles and high development difficulty. However, the method proposed in this paper overcomes these issues, improves FPGA development efficiency, reduces development costs, and provides designers with greater flexibility. Based on the model of an inverter control algorithm, this paper utilizes MATLAB software and employs Simulink’s embedded coder HDL Coder to automatically generate code from the model. Additionally, leveraging the FPGA-in-the-loop tool, a connection between the FPGA and the external simulation environment Simulink is established, enabling combined simulation of MATLAB and FPGA to accelerate the design and verification of the inverter control algorithm.

Adaptation of FPGA architecture for accelerated image preprocessing

The work is devoted to the topical problem at the intersection of communications theory, digital electronics and numerical analysis, namely the study of image processing methods implementation time on different architectures of computational devices, which are used for software and hardware acceleration. The subject of this article is the investigation of reconfigurable FPGA processing systems in the image processing area. The goal of this work is to create a reconfigurable FPGA-based image processing system and compare it with existing processing architectures. Task. To fulfill the requirements of this work, it is necessary to prepare a practical experiment as well as theoretical research of the proposed architecture; to investigate the process of creating a ZYNQ SoC-based image processing system; and to develop and benchmark the speed of execution for the given set of algorithms with the specific range of the picture resolution. Methods used: FPGA simulation, C++ parallel programming with OpenMP, NVIDIA CUDA, performance analysis tools. The result of this work is the development of a resilient SoC Zynq7000–based computing system with programmable logic and the possibility to load images to FPGA RAM using the resources of ARM core for further processing and output via HDMI video interface, which enables the change of PL configuration at any time during the processing process. Conclusions. The efficiency of the FPGA approach was compared with a parallel image processing method implementation with OpenMP and CUDA. An overview of the ZYNQ platform with specific details related to media processing is presented. The analysis of algorithm speed testing findings based on various outputs proved the advantage (of over 60 times) of hardware acceleration of image processing over software analogs. The obtained results may be used in the development of embedded SoC-based solutions that require acceleration of big data processing. Also, the achieved findings can be used during the process of finding a suitable embedded platform for a certain image-processing task, where high data throughput is one of the most desired requirements.

An efficient FDTD algorithm based on FPGA

the optimum device structures. where a huge number of iterative simulations are required. So, high-speed computers are needed. A design for an FPGA-based finite difference time domain (FDTD) simulator is proposed to accelerate the simulation process where the FDTD method is a remarkably effective computational electromagnetic technique for modelling electromagnetic space. The proposed technique is tested using the analysis of two-dimensional photonic crystal bend structure. The proposed FPGA simulator is 130x faster than the MATLAB program implemented in a PC with a 2.6 GHz processor and 40G RAM. Where, the relative error between FPGA proposed simulator and the MATLAB program was 7.52%. In this study memory architecture, parallelism, pipelining and fixed-point arithmetic have been studied and optimized. Implementing this structure will significantly improve computational speed, allowing it to be used in a wide range of other computational electromagnetics domains.

Modified single error correction orthogonal Latin square scheme to reduce parity check bits

Single-error correction (SEC) codes play a critical role in ensuring cache reliability. In ultra-high-speed caches, decoding delay is a key element to consider when selecting an SEC code. Single error correction orthogonal Latin square (SEC OLS) codes have the fastest decoding method. However, these codes impose a higher number of parity check bits compared to other SEC codes. These extra parity bits need to be stored with each data word in cache data array, which increased cache overheads. This may limit their adoption only to applications that can handle such overheads. In this paper, a modified SEC OLS coding scheme is proposed to reduce the number of stored parity check bits. Compared to the original SEC OLS codes, the proposed coding scheme reduces 25% and 31.3% of the stored parity bits when implemented to protect 16-bit and 64-bit data words, respectively. The results of FPGA and ASIC simulation and synthesis show that using the modified SEC to protect 16-bit words can be an attractive solution because it saves a significant amount of parities storage area, while running at a speed comparable to the original SEC OLS code. The implementation of the proposed SEC code to protect 64-bit words may still be suitable for area-sensitive cache applications that can cope with the slightly increased decoding delay.

Research On FPGA-based High-speed Data Optical Fiber Transmission

This article briefly introduces the principles and advantages of optical fiber transmission and the characteristics of the integrated IP core developed by Xilinx. Aiming at the advantages of optical fiber communication, Xilinx ZYNQ7000 series FPGA chips are used to design a high-speed data optical fiber transmission scheme based on FPGA. This solution uses the method of creating Block Design for design and development. It uses Verilog hardware description language and Vivado development software for experimental verification. In the FPGA simulation environment, the code is converted into a binary file and written to the chip through the JTAG interface for testing, and the experimental data is analyzed. As a result, it meets the design requirements of high-speed data transmission, which is of great significance to the research of high-speed data optical fiber transmission.

FPGA based Performance Analysis of Speed Control Permanent Magnet Synchronous Motor Drive with Pi and Fuzzy Logic Controller

Present research demonstrates an experimental work and simulation of FPGA based PMSM drives consists of PI and Fuzzy logic controller, for speed control under load, zero load and random change in load conditions. It also delineates the overall performance of a closed loop vector Permanent Magnet Synchronous Motor (PMSM) drive consisting of two loops, current for inner and speed for outer loops for better speed tracking systems. The resistive load which is connected across the armature of dc shunt motor and coupled with PMSM is varied. The resultant speed and torque are studied in details. Result showed that in case of fuzzy logic controller, the peak overshoot and settling time can be minimized. This FPGA based PMSM drives can be used for different paramount application under constant speed.

A Novel Square Root Algorithm and its FPGA Simulation

As a basic operation in elementary mathematics, square root operation is widely used in numerical calculation and digital signal processing. The square root operation is a nonlinear operation and cannot be solved directly on FPGA. Many previous square root algorithms have been proposed. This paper introduces several previous square root algorithms, then presents a novel square root algorithm which uses 16-bit integer input and 16-bit integer output. Using the idea of normalization, the square number is mapped to the range of 0-1, and the square root is approximated by the sum of numerical sequence. We discuss the proposed square root algorithm, error analysis. The proposed algorithm was programmed by the Verilog in Xilinx’s Vivado 17.2 software environment, and the simulation was verified on the Virtex-7 series chip. Compared with other square root algorithms, the algorithm only uses shifter, adders and sub-tractor. It does not involve complex operations, consumes less resources, and it’s suitable for implementation on FPGA.

Designing forward converters for data transmission systems in two-level RNS

We are considering the use of a two-stage Residue number system (RNS) in data transmission systems with a special set of modules {2l1, 2l2, 2l3,…, 2lp − 1}. We propose the forward converter with such type of RNS and demonstrate its advantage in hardware costs and delay. This article discusses the FPGA simulation of a forward conversion circuit to a two-stage RNS using adders and the standard modulo function and their comparison in terms of delay and hardware costs.

FPGA Implementation of Rake Receiver in Broadband Micro-power Wireless Communication System

Aiming at the problem that receiver performance is seriously degraded by multipath fading in multipath channel, a three-finger Rake receiver design scheme is proposed, based on Chirp spread spectrum technology for multipath search, delay estimation and phase estimation. Firstly, the windowed algorithm is adopted in multipath search to improve the accuracy of multipath search. Secondly, detecting the spacing between multipath peaks can realize the delay estimation of multipath signals. Finally, the multipath signals are merged to enhance the receiving effect, significantly improving the system’s block error rate performance under the multipath channel environment. Matlab simulation shows that adding a Rake receiver in the system can improve performance by about 1.2dB. A multi-switching mechanism is applied in FPGA implementation, in order to reduce the hardware power consumption. FPGA simulation results verify rationality and correctness of the design, indicating that the system meets the requirements of block error rate less than 1% in actual transmission, when the signal-to-noise ratio is -2dB.

Design an All Digital PLL with Ripple Reduction Technique

The article describes about the design and implementation of advance version of Phase Lock Loop (PLL) is All Digital PLL. Research work is on ADPLL where parameter ripple is reduced by applying the technique of ripple reduction technique. Ripple reduction technique reduces the use of Kth counter, Kth counter comes under consideration when enable is ON. Phase locked loops are most widely used in communication system. Most of the PLL’s that are used currently are hybrid type PLL’s where all the blocks are assumed to be digital. The circuit design of ADPLL consists of Digital Controlled Oscillator (DCO), loop filter and Phase Frequency detector (PFD). Here phase detector used is Ex-or gate, for loop filter, Kth counter is used and Increment/Decrement circuit is used as DCO. Divide-by-N counter is used for feedback system. The output of the DCO is going in the PFD through the feedback network. Xilinx Vivado suit 2018.2 tools is used for simulating Verilog code. Board chosen in vivado is zed board Zynq. First, with the help of circuit diagram of ADPLL Verilog code is being written on project window. After compilation of code it is simulated with the help of test bench. After that it is going to be implemented and verified with the board zedboard. Number of LUTs used are 32 and Flip Flops used are 35. This paper presents an all digital approach for the design, simulation, synthesis and implementation of FPGA based ADPLL centered at 195.31 KHz using Verilog HDL code. The proposed design methodology resulted in reduction of ripple, power dissipation, junction temperature of board. Proposed research work further can be used in communication for frequency synthesizer. Any system whether it is from communication or digital etc ADPLL is common to use for ripple reduction at its output. So ADPLL is basic building block in any type of communication system.

Programming Spiking Neural Networks on Intel’s Loihi

Loihi is Intel’s novel, manycore neuromorphic processor and is the first of its kind to feature a microcode-programmable learning engine that enables on-chip training of spiking neural networks (SNNs). The authors present the Loihi toolchain, which consists of an intuitive Python-based API for specifying SNNs, a compiler and runtime for building and executing SNNs on Loihi, and several target platforms (Loihi silicon, FPGA, and functional simulator). To showcase the toolchain, the authors describe how to build, train, and use a SNN to classify handwritten digits from the MNIST database.

Designing for FPGAs in the Cloud

Editor’s note: This article proposes a flow to provision FPGAs from a pool of cloud resources. The proposed flow can lead to more efficient sharing of limited FPGA resources by enabling FPGA development and simulation in virtual machines. —Mustafa Ozdal, Bilkent University

Designing Efficient Two-Level Reverse Converters for Moduli Set $$\{2^{2n+1}-1,2^{2n},2^{n}-1\}$$ { 2 2 n + 1 - 1 , 2 2 n , 2 n - 1 }

Residue number system is a non-weighted system in which some arithmetic operations are performed parallelly. A factor that affects the system’s performance is the complexity of converters, as the complexity of reverse converter should not discomfit the earned speed of parallelly performing arithmetic unit. In this paper, two efficient reverse converters are proposed for moduli set $$\{2^{2n+1}-1,2^{2n},2^{n}-1\}$$ by using two-level method and mixed-radix conversion algorithm. Both unit gate model and simulation are used to have an efficient comparison. The novel converters and the recently presented reverse converters with similar dynamic range were implemented in Hardware Description Language on Xilinx 13.1 FPGA simulator. Area and delay of each converter were measured for various dynamic range up to 256 bits. As the results indicated, the novel proposed area-efficient converter and delay-efficient converter indicate an improvement about 8 and 14%, respectively, in terms of time complexity comparing to the recently presented design.

Simulation of FPGA controlled Single Stage Boost Inverter for the Applications of Grid Connected Photovoltaic System

Improving the efficiency, reducing the cost and maintaining the power quality of a grid tied with Photovoltaic (PV) system are the important aspects of the present day research. The efficiency of power conversion can be improved by reducing the number of stages. In this paper, a single stage boost inverter topology fed from PV array is used and connected to a single phase grid. Less number of switching components is used in this topology compared to conventional technique and hence, the converter losses are reduced. This can also be very well extended to utility grid system. Further, the proposed topology includes battery backup unit which consists of a DC-DC converter to overcome the variations of Voltage based Maximum Power Point (VMPP) of PV array because of the variations in solar irradiance. The proposed system uses the current control approach which has zero steady state tracking error to control the single stage boost inverter. The proposed system offers many advantages such as low cost, high efficiency, compactness and high quality of output power. Design procedure and simulation results are obtained from MATLAB/SIMULINK and the experimental results are obtained from the model developed in the laboratory. The entire system is controlled by SPATRAN 3A FPGA board.

FPGA Accelerator of Algebraic Quasi Cyclic LDPC Codes for <sc>nand</sc> Flash Memories

In this article, the authors implement an FPGA simulator that accelerates the performance evaluation of very long QC-LDPC codes, and present a novel 8-KB LDPC code for NAND flash memory with better performance.

Real-time hand gesture recognition in FPGA

Hand Gesture has been used in different applications and also implemented on different platforms. A faster and smooth approach with reasonable accuracy is always needed to make smart devices smarter and faster. This paper describes a novel procedure of hand gesture recognition using Principal Component Analysis (PCA) implemented in FPGA Simulator. The simulation was done using co-simulation tool of Simulink with Xilinx System Generator (XSG). Hardware-Software co-simulation is a good methodology which assures accurate and rapid prototyping leading to faster simulation times for heterogeneous systems design. Total processing time for the designed hardware was found to be 530ns using FPGA having the operating frequency of 100MHz.

Design and Simulation of FPGA Based Digital Controller for Single Phase Boost PFC Converter

Design and Simulation of FPGA Based Digital Controller for Single Phase Boost PFC Converter

Estimation of channel impulse response and FPGA simulation

Estimation of channel impulse response and FPGA simulation