FPGA Implementation Research Articles

A fog-based anonymous authentication scheme with location privacy for wireless body area network with FPGA implementation

A fog-based anonymous authentication scheme with location privacy for wireless body area network with FPGA implementation

VECTOR-LOGICAL FAULT SIMULATION

Context. The main idea is the creation of vector-logical in-memory computing (VLC), which uses only read-write transactions on the address memory for faults-as-addresses simulation. There is no traditional logic. VLC is free from processor commands and ALU for computing organization and is therefore focused on implementation in SoC and FPGA. A vector-logical method of deductive matrix synthesis for the transportation of input faults, which has a quadratic computational complexity, is proposed. An inmemory simulator-automata for vector-deductive faults-as-addresses simulation, which based on read-write transactions for implementation in SoC is proposed. Objective. Development of a vector deductive method of fault simulation based on primitive read-write transactions for the analysis of logic circuits. Method. An input test set and a logical functionality vector are used. The proposed method is a development of the deductive vectors’ synthesis algorithm based on the truth table. The deductive matrix is intended for the synthesis and verification of tests using parallel simulation of faults-as-addresses combinations, based on read-write transactions over bits of deductive vectors in memory. Results. A vector method of the deductive matrices synthesis for the transportation of input faults vectors to the output of the element, was proposed. Data structures have been developed for parallel faults simulation of digital circuits based on a primitive readwrite transaction in matrix memory, where combinations of faults serve as address-columns. A sequencer of five blocks, that constitute a vector-logic computing, connected with deductive faults simulation based on read-write transactions, is proposed. Verification of models and methods on test examples has been performed. Conclusions. The scientific novelty consists in the development of the following innovative solutions: 1) a vector-logic method of synthesis of the deductive vectors matrix for parallel simulation of combinations of input faults-as-addresses, is proposed for the first time; 2) an automata for vector-deductive faults-as-addresses simulation, on the basis of read-write transactions, which is oriented for implementation in FPGA LUT, embedded online simulator SoC, as a core for faults simulation of RTL-level digital systems, was proposed for the first time; 3) the demonstration of the technological advantages of the vector-logic synthesis of deductive matrices is performed on numerous examples of traditional and RTL-logic, which accentuate the manufacturability of vectors in comparison with analytical deductive formulas during simulators construction; 4) a matrix of deductive vectors, as a set of vectorcolumns of Boolean derivatives is used to construct minimal tests for logical elements; 5) the recursive formula for the synthesis of the permutation of coordinates matrix in the logical activity vector makes it possible to significantly simplify the obtaining of the deductive matrix for faults-as-addresses simulation. The practical significance lies in the fact that the in-memory simulator will allow to obtain the speed of faults simulation of real digital blocks for SoC at the level of hundreds of nanoseconds. Complexity estimates of the corresponding algorithms are given.

FPGA Centric Attention Based Deep Learning Network Evoked Chaotic Encryption to Mitigate Side Channel Attacks

Security concerns are growing, especially in applications where sensitive information is sent (such as health care devices, credit cards, and even Internet of Things (IoT) nodes), even while these developments bring in a modern revolution. This is due to the constant scaling of technologies, which has now been incredibly useful for delivering the new trend of development in the numerous domains such as communications, semiconductors, health care, and automation. Even when cutting-edge standard encryption algorithms are used in smart devices, the principal threats, such as Side-Channel Attacks (SCA) and Correlation Power Analysis (CPA), increase the susceptibility of encrypted cipher text to attacks. In order to defend against side channel assaults, the usefulness of deep learning algorithms combined with chaotic principles is examined in this paper. Scroll Mapping (SM) and Attention-Evoked Long Short-Term Memory (AE-LSTM) are used in the proposed study to effectively safeguard sensitive data while consuming little power. The most promising advancements in terms of all security metrics and hardware capabilities for obtaining high-speed performances are shown by experimental findings on an FPGA implementation of a suggested framework.

BSAPM: BlockChain based secured authentication protocol for large scale WSN with FPGA implementation

According to state-of-the-art, several multiple base station-based authentication and key agreement protocols exist. Still, most of the protocols are computationally inefficient and suffer from several potential attacks. In this research work, we consider WSN architecture, where multiple base stations are located in a distributed way. After that, we proposed a blockchain-based authentication and key agreement protocol for establishing secure communication. This protocol utilizes a smart contract facility during the registration of the sensor node. Our work also stores records of the sensor node in blockchain network. Most importantly, we have verified the proposed protocol using FPGA implementation, which further confirms the correctness of the generated session keys. BSAPM is demonstrated in terms of security threats using the Scyther tool, and we have also shown formal security analysis using the Real-or-Random(ROR) model. The informal security analysis demonstrates the protection against security threats. BSAPM is better in terms of communication, computation overheads, and functionality features when compared to the related other competitive schemes.

Fixed-point FPGA Implementation of the FFT Accumulation Method for Real-time Cyclostationary Analysis

The spectral correlation density (SCD) is an important tool in cyclostationary signal detection and classification. Even using efficient techniques based on the fast Fourier transform (FFT), real-time implementations are challenging because of the high computational complexity. A key dimension for computational optimization lies in minimizing the wordlength employed. In this article, we analyze the relationship between wordlength and signal-to-quantization noise in fixed-point implementations of the SCD function. A canonical SCD estimation algorithm, the FFT accumulation method (FAM) using fixed-point arithmetic, is studied. We derive closed-form expressions for SQNR and compare them at wordlengths ranging from 14 to 26 bits. The differences between the calculated SQNR and bit-exact simulations are less than 1 dB. Furthermore, an HLS-based FPGA design is implemented on a Xilinx Zynq UltraScale+ XCZU28DR-2FFVG1517E RFSoC. Using less than 25% of the logic fabric on the device, it consumes 7.7 W total on-chip power and has a power efficiency of 12.4 GOPS/W, which is an order of magnitude improvement over an Nvidia Tesla K40 graphics processing unit (GPU) implementation. In terms of throughput, it achieves 50 MS/sec, which is a speedup of 1.6 over a recent optimized FPGA implementation.

E$${^2}$$CSM: efficient FPGA implementation of elliptic curve scalar multiplication over generic prime field GF(p)

E$${^2}$$CSM: efficient FPGA implementation of elliptic curve scalar multiplication over generic prime field GF(p)

An FPGA Architecture for the RRT Algorithm Based on Membrane Computing

This paper investigates an FPGA architecture whose primary function is to accelerate parallel computations involved in the rapid-exploring random tree (RRT) algorithm. The RRT algorithm is inherently serial, while in each computing step there are many computations that can be executed simultaneously. Nevertheless, how to carry out these parallel computations on an FPGA so that a high degree of acceleration can be realized is the key issue. Membrane computing is a parallel computing paradigm inspired from the structures and functions of eukaryotic cells. As a newly proposed membrane computing model, the generalized numerical P system (GNPS) is intrinsically parallel; so, it is a good candidate for modeling parallel computations in the RRT algorithm. Open problems for the FPGA implementation of the RRT algorithm and GNPS include: (1) whether it possible to model the RRT with GNPS; (2) if yes, how to design such an FPGA architecture to achieve a better speedup; and (3) instead of implementing GNPSs with a fixed-point-number format, how to devise a GNPS FPGA architecture working with a floating-point-number format. In this paper, we modeled the RRT with a GNPS at first, showing that it is feasible to model the RRT with a GNPS. An FPGA architecture was fabricated according to the GNPS-modeled RRT. In this architecture, computations, which can be executed in parallel, are accommodated in different inner membranes of the GNPS. These membranes are designed as Verilog modules in the register transfer level model. All the computations within a membrane are triggered by the same clock impulse to implement parallel computing. The proposed architecture is validated by implementing it on the Xilinx VC707 FPGA evaluation board. Compared with the software simulation of the GNPS-modeled RRT, the FPGA architecture achieves a speedup of a 104 order of magnitude. Although this speedup is obtained on a small map, it reveals that this architecture promises to accelerate the RRT algorithm to a higher level compared with the previously reported architectures.

Bifurcation Analysis, Synchronization and FPGA Implementation of a New 3-D Jerk System with a Stable Equilibrium

This research paper addresses the modelling of a new 3-D chaotic jerk system with a stable equilibrium. Such chaotic systems are known to exhibit hidden attractors. After the modelling of the new jerk system, a detailed bifurcation analysis has been performed for the new chaotic jerk system with a stable equilibrium. It is shown that the new jerk system has multistability with coexisting attractors. Next, we apply backstepping control for the synchronization design of a pair of new jerk systems with a stable equilibrium taken as the master-slave chaotic systems. Lyapunov stability theory is used to establish the synchronization results for the new jerk system with a stable equilibrium. Finally, we show that the FPGA design of the new jerk system with a stable equilibrium can be implemented using the FPGA Zybo Z7-20 development board. The design of the new jerk system consists of multipliers, adders and subtractors. It is observed that the experimental attractors are in good agreement with simulation results.

Methodology for CNN Implementation in FPGA-Based Embedded Systems

The increasing interest in Convolutional Neural Networks (CNNs) is driving the study and design of different implementations for a variety of platforms, each intended to optimize performance, power consumption, or latency, according to the application’s needs. While GPUs have dominated the high-performance terrain, FPGAs have proved to be a promising alternative due to their relatively high performance, reduced power consumption and costs, compared with GPUs. The main concern regarding FPGA implementations lies in the effort needed to develop the systems and difficulties reusing or combining designs by different authors, due to the highly heterogeneous architectures used in each project. This work proposes a methodology and a high-level architecture designed for CNN implementations in FPGAs, that eases the development process, allows the reusability of designs, and helps to maximize performance, minimize latency, reduce resource utilization and avoid possible bottlenecks, while allowing high design flexibility. This proposal is validated by implementing a set of blocks that are later used to build different CNNs.

Feature-Based Scanning LiDAR-Inertial Odometry Using Factor Graph Optimization

Localization of a mobile robot in the absence of an absolute position sensor often relies on techniques such as visual or lidar-inertial odometry. While lidar has many advantages, the most capable sensors use scanning mechanisms, leading to motion-distorted scans. Previous strategies used to account for robot motion when performing state estimation and outlier rejection have drawbacks for use on highly dynamic, resource-constrained robots such as spacecraft during descent and landing. In this paper we develop a novel probabilistic factor for the inclusion of scanning lidar features, and an accompanying outlier rejection methodology. By using well-established, efficient feature tracking techniques, our image processing front end is both reliable and amenable to FPGA implementation, both of which are critical for operation on a spacecraft. We demonstrate our technique on a dataset from simulated planetary descent and landing. The results show that our system can be used to perform accurate lidar-inertial odometry, even in highly dynamic scenarios.

Efficient Implementation of Spontaneous Calcium Oscillations in the Central Nervous System on Reconfigurable Digital Boards

Biological systems in case of real-time state and also large-scale simulation approach are interesting and challenge-based due to different aspects of nonlinear mathematical modeling that can describe the interactions of biological blocks. Thus, hardware circuit designing of these basic blocks in the Central Nervous System (CNS) can be an important field in case of achieving high performance neuromorphic system emulator. This paper presents a high-speed, low-cost, and efficient digital circuit for emulating the plausible calcium-dynamic-based model of astrocyte which has spontaneous oscillations. The nonlinear high-cost functions of the complex astrocyte model are reformulated using the power-2 based low-cost terms using optimized exhaustive search algorithm. Subsequently, the proposed model is simulated in case of validating the presented model and new optimized functions. Finally, the proposed model is physically realized in hardware case using Virtex 4 FPGA platform to test and validate final circuits. FPGA implementation results confirmed the ability of the design to emulate biological cell behaviours in detail with high accuracy. The proposed hardware consumes maximum <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\%$</tex-math> </inline-formula> of the all resources of a Virtex 4 board. Additionally, timing analysis and synthesize report represent that the proposed model works in a high frequency of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\rm 371.56$</tex-math> </inline-formula> MHz. Moreover, to validate the results of implementation, the proposed model is compared with the original model and other similar works in terms of accuracy, speed-up, and maximum number of implemented astrocyte.

Design and FPGA Implementation of Pre-computation Based Radix-4 Hyperbolic CORDIC for Direct Digital Synthesis

Design and FPGA Implementation of Pre-computation Based Radix-4 Hyperbolic CORDIC for Direct Digital Synthesis

Efficient Digital Implementation of a Multirate-Based Variable Fractional Delay Filter for Wideband Beamforming

In this brief, we propose a FPGA implementation of a novel Variable Fractional Delay (VFD) filter architecture for digital wideband (hundred of MHz or more) beamforming applications. The proposed architecture is based on a multirate structure that allows reaching high performance in terms of amplitude and group delay with a significant reduction in design complexity. Usually, the antenna’s beams are modified by introducing precise delays that can be multiples or fractions of the sampling period. The most used structures for realizing this operation are Farrow filters but, for wideband applications, the classical Farrow structure may require a huge amount of resources. A common solution to simplify the Farrow filter architecture is interpolation. However, this solution requires an increase of the clock frequency which is not always possible. In this context, our multirate approach mitigates the limitations in terms of computational complexity avoiding the requirement to increase of the clock frequency, while still exhibiting great performance. A comparison between a reference design based on the proposed approach and the literature is also provided. The experimental results confirm that the proposed architecture, characterized by a computational complexity similar to other works, exhibits better performance without the need to increase the clock frequency.

FPGA Implementation of Flexible Successive-Cancellation Polar Decoder

Kanal kapasitesi, bir kanalın iletilebileceği maksimum bit hızını ifade eder. Kutupsal kodlar, simetrik ikili girişli, hafızasız kanallar için sonsuz blok uzunluğunda kanal kapasitesine erişebilen ilk hata düzeltme kodlarıdır. Kutupsal kodların bu başarımı ile 5. Nesil Yeni Radyo Haberleşme standardında kullanımına karar verilmiştir. Bu çalışmada, farklı blok uzunluklarında ve farklı kod oranlarında kutupsal kodların, ardışık-çıkarım (successive-cancellation) kod çözücü algoritması alanında programlanabilir kapı dizileri (Field-programmable gate array, FPGA) ile gerçeklemesi anlatılmıştır.

FPGA Implementation of Parameter-Switching Scheme to Stabilize Chaos in Fractional Spherical Systems and Usage in Secure Image Transmission

The main objective of this work was to implement the parameter-switching chaos control scheme for fractional-order spherical systems and develop a chaos-based image encryption and transmission system. The novelty in the developed secure communication system is the application of the parameter-switching scheme in the decryption of RGB and grayscale images, which undergo one round of encryption using the chaotic states of the fractional system and a diffusion process. The secure communication system has a synchronized master and slave topology, resulting in transmitter and receiver systems for encrypting and decrypting images, respectively. This work was demonstrated numerically and also implemented on two FPGAs, namely Artix-7 AC701 and Cyclone V. The results show that the parameter-switching scheme controls chaos in the fractional-order spherical systems effectively. Furthermore, the performance analysis of the image encryption and transmission system shows that there is no similarity between the original and encrypted images, while the decryption of the encrypted images is without a loss of quality. The best result in terms of the encryption was obtained from the chaotic state x of the fractional-order system, with correlation coefficients of 0.0511 and 0.0392 for the RGB and grayscale images, respectively. Finally, the utilization of the FPGA logical resources shows that the implementation on Artix-7 AC701 is more logic-efficient than on Cyclone V.

A deep learning-based side channel attack model for different block ciphers

Recently, there has been renewed interest in the combination of deep learning and side-channel analysis (SCA). Many previous studies have transformed the traditional SCA into a classification problem in deep learning. This paper considers it as a regression problem based on the principle that the changes of some circuit states are related to the special operation in cipher. We proposed a regression model which consists of an initial layer, a deep feature mining dense layer, and a regression layer. In the term of dataset, there are two sources of data: the raw ASCAD power traces and the data sampled from FPGA implementation of AES and PRESENT. The mainly advantages of this model and regression task processing method is that it can adapt to different cryptographic algorithms on the same hardware device. Moreover, the experimental result that the model can significantly improve the attack accuracy of SCA. In ASCAD, its prediction accuracy achieves 2.90% and 3.63% for two different intermediate values, and their correlation coefficient evaluation 0.873, 0.840. In FPGA power dataset, their prediction and correlation coefficient are 3%, 4%, and 0.963, 0.987 respectively.

A family of new generalized multi-scroll Hamiltonian conservative chaotic flows on invariant hypersurfaces and FPGA implementation

A family of new generalized multi-scroll Hamiltonian conservative chaotic systems(HCCSs) are firstly found by investigating Hamiltonian energy of a Hamiltonian conservative chaotic system. And the novelty of the family of new generalized multi-scroll HCCSs is that they are on some invariant hypersurfaces depending on Hamiltonian energy. Subsequently, some numerical analysis are given to show multi-scroll chaotic dynamics and complex characteristics of the family of new generalized multi-scroll HCCSs. Finally, FPGA circuits are employed to implement the family of new generalized multi-scroll HCCSs, which not only physically show the existence of multi-scroll dynamics, but also provide a family of new pseudo-random signal generators for engineering applications.

FPGA Implementation for Elliptic Curve Cryptography Algorithm and Circuit with High Efficiency and Low Delay for IoT Applications.

The Internet of Things requires greater attention to the security and privacy of the network. Compared to other public-key cryptosystems, elliptic curve cryptography can provide better security and lower latency with shorter keys, rendering it more suitable for IoT security. This paper presents a high-efficiency and low-delay elliptic curve cryptographic architecture based on the NIST-p256 prime field for IoT security applications. A modular square unit utilizes a fast partial Montgomery reduction algorithm, demanding just a mere four clock cycles to complete a modular square operation. The modular square unit can be computed simultaneously with the modular multiplication unit, consequently improving the speed of point multiplication operations. Synthesized on the Xilinx Virtex-7 FPGA platform, the proposed architecture completes one PM operation in 0.08 ms using 23.1 k LUTs at 105.3 MHz. These results show significantly better performance compared to that in previous works.

Experimental Survey of FPGA-Based Monolithic Switches and a Novel Queue Balancer

This paper studies small to medium-sized monolithic switches for FPGA implementation and presents a novel switch design that achieves high algorithmic performance and FPGA implementation efficiency. Crossbar switches based on virtual output queues (VOQs) and variations have been rather popular for implementing switches on FPGAs, with applications in network switches, memory interconnects, network-on-chip (NoC) routers etc. The implementation efficiency of crossbar-based switches is well-documented on ASICs, though we show that their disadvantages can outweigh their advantages on FPGAs. One of the most important challenges in such input-queued switches is the requirement for iterative scheduling algorithms. In contrast to ASICs, this is more harmful on FPGAs, as the reduced operating frequency and narrower packets cannot “hide” multiple iterations of scheduling that are required to achieve a modest scheduling performance.Our proposed design uses an output-queued switch internally for simplifying scheduling, and a queue balancing technique to avoid queue fragmentation and reduce the need for memory-sharing VOQs. Its implementation approaches the scheduling performance of a state-of-the-art FPGA-based switch, while requiring considerably fewer resources.

Multistage FPGA Least Mean Squares Filters Suppressing Multiple Narrowband Radio-Frequency Interferences in the Radio Detection of Cosmic Rays

The article presents the FPGA implementation of 256- and 768-stage Least Mean Squares filters with rectangular, Hamming and Kaiser windows to suppress at least 10 narrow-bands RFIs. The analysis shows extremely high efficiency Radio Frequency Interference (RFI) elimination. 9-bit real cosmic ray data from the Auger Engineering Radio Array (AERA) was used as patterns and mixed with 14-bit multiple narrow-band RFIs. They were hidden deep within RFI’s background. After the cleaning process, the patterns were brought out and are practically without contamination.