FPGA Fabric Research Articles

An Approach to the Systematic Characterization of Multitask Accelerated CNN Inference in Edge MPSoCs

Deep Learning is ubiquitous today and is increasingly moving from the cloud down to the edge of networked infrastructures, where it enables embedded applications to perform complex inference tasks close to the data sources, reducing long-distance data movement and alleviating the need for a powerful cloud infrastructure. Edge-class multi-processor system on chip (MPSoC) devices featuring an on-chip FPGA fabric offer key advantages for Deep Learning inference tasks, especially for complex applications where multiple models may be run concurrently in the same platform. In this work, we propose an approach and a practical framework for the systematic characterization of multithreaded Deep Learning inference on edge FPGA MPSoCs. We instantiate the framework into a real-world MPSoC platform, targeting Xilinx Vitis-AI as a representative example of a commercial Deep Learning acceleration toolkit for edge environments. We design a comprehensive experimental campaign and apply it to the platform for several convolutional neural networks, each trained on three different datasets. We show that our approach can be used for both hardware- and software-level analysis of a target system. Among other findings, the analysis revealed a suboptimal behavior of the underlying toolkit runtime, involving the utilization of the accelerator cores and the uneven software latency of the support library, influenced by the shapes of the input tensors.

Evaluating the Impact of Using Multiple-Metal Layers on the Layout Area of Switch Blocks for Tile-Based FPGAs in FinFET 7nm

A new area model for estimating the layout area of switch blocks is introduced in this work. The model is based on a realistic layout strategy. As a result, it not only takes into consideration the active area that is needed to construct a switch block but also the number of metal layers available and the actual dimensions of these metals. The model assigns metal layers to the routing tracks in a way that reduces the number of vias that are needed to connect different routing tracks together while maintaining the tile-based structure of FPGAs. It also takes into account the wiring area required for buffer insertion for long wire segments. The model is evaluated based on the layouts constructed in the ASAP7 FinFET 7nm Predictive Design Kit. We found that the new model, while specific to the layout strategy that it employs, improves upon the traditional active-based area estimation models by considering the growth of the metal area independently from the growth of the active area. As a result, the new model is able to more accurately estimate the layout area by predicting when the metal area will overtake the active area as the number of routing tracks is increased. This ability allows the more accurate estimation of the true layout cost of FPGA fabrics at the early floor planning and architectural exploration stage; and this increase in accuracy can encourage a wider use of custom FPGA fabrics that target specific sets of benchmarks in future SOC designs. Furthermore, our data indicate that the conclusions drawn from several significant prior architectural studies remain to be correct under FinFET geometries and wiring area considerations despite their exclusive use of active-only area models. This correctness is due to the small channel widths, around 30–60 tracks per channel, of the architectures that these studies investigate. For architectures that approach the channel width of modern commercial FPGAs with more than 100–200 tracks per channel, our data show that wiring area models justified by detailed layout considerations are an essential addition to active area models in the correct prediction of the implementation area of FPGAs.

Diagnosis of Malicious Bitstreams in Cloud Computing FPGAs

Multi-tenant FPGAs are increasingly being used in cloud computing technologies. Users are able to access the FPGA fabric remotely to implement custom accelerators in the cloud. However, the sharing of FPGA resources by untrusted third-parties can lead to serious security threats. Attackers can configure a portion of the FPGA with a malicious bitstream. Such malicious use of the FPGA fabric may lead to severe voltage fluctuations and denial-of-service. In this work, we consider FPGAs that support time-based multi-tenancy i.e., a single user has access to the FPGA at a time. We propose a convolutional neural network (CNN)-based approach to detect malicious RO-like circuits that are configured on an FPGA by learning features from the data-series representation of the bitstreams of malicious circuits. We use the classification accuracy, true-positive rate, and false-positive rate metrics to quantify the effectiveness of CNN-based classification of malicious bitstreams. Our threat model includes a variety of power-wasting circuits that are used to configure FPGAs in the cloud. We propose a two-stage malicious bitstream detection framework for classification and diagnosis of the type of malicious circuit implemented by a particular bitstream. We further propose a novel window-merging technique to improve model performance in the second stage of the detection framework. Experimental results on Xilinx FPGAs demonstrate the effectiveness of the proposed method.

Shift Register, Reconvergent-Fanout (SiRF) PUF Implementation on an FPGA

Physical unclonable functions (PUFs) are gaining traction as an attractive alternative to generating and storing device keying material over traditional secure non-volatile memory (NVM) technologies. In this paper, we propose an engineered delay-based PUF called the shift-register, reconvergent-fanout (SiRF) PUF, and present an analysis of the statistical quality of its bitstrings using data collected from a set of FPGAs subjected to extended industrial temperature-voltage environmental conditions. The SiRF PUF utilizes the Xilinx shift register primitive and an engineered network of logic gates that are designed to distribute signal paths over a wide region of the FPGA fabric using a MUXing scheme similar in principle to the shift-rows permutation function within the Advanced Encryption Standard algorithm. The shift register is utilized in a unique fashion to enable individual paths through a Xilinx 5-input LUT to be selected as a source of entropy by the challenge. The engineered logic gate network utilizes reconvergent-fanout as a means of adding entropy, eliminating bias and increasing uncertainty with respect to which paths are actually being timed and used in post-processing to produce the secret key or authentication bitstring. The SiRF PUF is a strong PUF build on top of a network with 10’s of millions of possible paths.

Securing SoCs With FPGAs Against Rowhammer Attacks

Heterogeneous SoCs integrate FPGAs and microprocessor cores on the same fabric to accelerate applications, such as cryptography and deep learning. Since FPGAs share resources with the microprocessor cores, they can launch noncacheable synchronous DRAM (SDRAM) transactions through direct FPGA-to-microprocessor SDRAM interface. Therefore, if the FPGA 3rd party IPs (3PIPs) are malicious, they can launch rowhammer attacks on the SDRAM. Today’s countermeasures based on performance counters cannot detect these attacks because memory transactions from FPGAs do not pass through the cache. In addition, today’s countermeasures that count the frequency of activation of memory rows cannot identify the intellectual property (IP) that launches the attack from the FPGA. We present a security solution that monitors the SDRAM transactions from IPs on the FPGA to each bank of the microprocessor SDRAM through the FPGA-to-microprocessor SDRAM interface. The proposed monitor is implemented on the FPGA fabric. It can detect attempts to launch a rowhammer attack before it causes bit flips in the SDRAM. It utilizes 6.3% of the adaptive logic modules (ALMs) available in an Intel Cyclone V FPGA, when multiple IPs are monitored.

THx2 Programmable Logic Block Architecture for Clockless Asynchronous FPGAs

To address some of the challenges of asynchronous design, we propose a new, decomposable asynchronous logic block architecture based on our TH<inline-formula> <tex-math notation="LaTeX">$x2$ </tex-math></inline-formula> programmable threshold cell, and we use it to implement common threshold functions found in asynchronous, null convention logic circuits. At a minimum, programmable gate arrays require a programmable logic cell that can implement a complete set of logic. It is well known that a NAND function forms a complete set of logic, and in null convention logic, the TH12 and TH22 threshold cells are used to form a basic two-input NAND function. The TH<inline-formula> <tex-math notation="LaTeX">$x2$ </tex-math></inline-formula> threshold cell is capable of performing both TH12 and TH22 operations, so it too forms a complete set of logic. In this paper, we present our eight-transistor mask-programmable gate array logic cell, 16-transistor field-programmable gate array logic cell, and new decomposable field-programmable gate array logic block architecture, all based on the TH<inline-formula> <tex-math notation="LaTeX">$x2$ </tex-math></inline-formula> threshold cell and suitable for implementing null convention logic asynchronous functions. To minimize the TH<inline-formula> <tex-math notation="LaTeX">$x2$ </tex-math></inline-formula> threshold cell area for both TH12 and TH22 modes, we designed a layout with common Euler paths and no diffusion breaks for both modes. The highly compact nature of the TH<inline-formula> <tex-math notation="LaTeX">$x2$ </tex-math></inline-formula> threshold cell&#x2013;along with the symmetry of the mask- and field-programmable gate array logic cells&#x2013;made it an ideal candidate for an asynchronous field-programmable logic block structure. This paper is part of an ongoing project, and it only addresses the programmable logic block architecture, not a complete FPGA fabric.

Inducing Non-uniform FPGA Aging Using Configuration-based Short Circuits

This work demonstrates a novel method of accelerating FPGA aging by configuring FPGAs to implement thousands of short circuits, resulting in high on-chip currents and temperatures. Patterns of ring oscillators are placed across the chip and are used to characterize the operating frequency of the FPGA fabric. Over the course of several months of running the short circuits on two-thirds of the reconfigurable fabric, with daily characterization of the FPGA 6 performance, we demonstrate a decrease in FPGA frequency of 8.5%. We demonstrate that this aging is induced in a non-uniform manner. The maximum slowdown outside of the shorted regions is 2.1%, or about a fourth of the maximum slowdown that is experienced inside the shorted region. In addition, we demonstrate that the slowdown is linear after the first two weeks of the experiment and is unaffected by a recovery period. Additional experiments involving short circuits are also performed to demonstrate the results of our initial experiments are repeatable. These experiments also use a more fine-grained characterization method that provides further insight into the non-uniformed nature of the aging caused by short circuits.

Mapping Processing Elements of Custom Virtual CGRAs onto Reconfigurable Partitions

FPGAs can provide application-specific acceleration for computationally demanding tasks. However, they are rarely considered general-purpose platforms due to low productivity of software development and long reconfiguration time. These problems can be mitigated by implementing a coarser overlay atop the FPGA fabric. Combining this approach with partial reconfiguration allows for the modification of individual processing elements (PEs) of the virtual architecture without altering the rest of the system. Module relocation can be used to share implementation details between functionally equivalent PEs that use identical sets of resources, thus eliminating redundant placement and routing runs. Proper floorplanning is crucial for virtual Coarse-Grained Reconfigurable Architectures (CGRAs) with relocatable PEs considering their tendency to use nearest-neighbor connection patterns. It requires solving two problems—finding identical regions in the FPGA fabric and assigning individual partitions to certain locations. This article presents minor improvements of a state-of-the-art solution for the first and proposes a novel technique for solving the other. The proposed automated floorplanner uses modified breadth-first search with direction-based penalties to create initial floorplan consistent with geometry of logical array, then improves the result with 2-opt local optimization. Compared to simulated annealing solutions, the proposed approach allows for the reduction in the floorplanning time by two to three orders of magnitude without compromising the quality of the results.

Embedded Real-Time Simulator for Sensorless Control of Modular Multi-Level Converters

This paper suggests the application of an embedded real-time simulator (eRTS) in the context of voltage–sensorless control of a modular multilevel power converter (MMC). This eRTS acts as an observer and ensures digital redundancy in the case of any fault occurring among the capacitor voltage sensors of the MMC submodules. Hence, in such a faulty situation, the MMC controller switches from the measured voltages to their estimated counterparts. As for the digital implementation, to ensure a high level of integration of the overall control system, the Xilinx Zynq-7020 system-on-chip field programmable gate array (SoC-FPGA) device was used. The controller was implemented in the hardwired ARM Cortex-A9 processor, with a 100 µs time step. Regarding the time-sensitive blocks (PWM, eRTS and measurements filtering), a full hardware implementation was privileged, using the FPGA fabric. The execution time of these blocks was 710 ns with a 100 MHz system clock, and the synchronization with the analog to digital acquisition chain was made with a 5 µs time resolution. The whole proof-of-concept system was experimentally tested, including the time/area evaluation of the implemented designs and the experimental validation of the eRTS estimations in both healthy and faulty scenarios.

A Linux-based support for developing real-time applications on heterogeneous platforms with dynamic FPGA reconfiguration

Computing platforms for next-generation cyber–physical systems are evolving towards heterogeneous architectures comprising different processing elements and hardware accelerators. In particular, SoC-FPGA platforms, including multiple general-purpose processing cores tightly coupled with an FPGA fabric, represent an attractive solution due to their flexibility, efficiency, and timing predictability. On these platforms, dedicated hardware accelerators implemented on the FPGA fabric can offload computationally intensive activities from general-purpose processing cores. Furthermore, dynamic partial reconfiguration allows virtualizing the FPGA resources by sharing them among multiple hardware accelerators over time.Although very promising, FPGA-based hardware acceleration also introduces new challenges, such as managing and scheduling multiple concurrent acceleration and reconfiguration requests. The FRED framework has been proposed to address these challenges while preserving the predictability required by real-time systems. FRED is based on a device model that matches the capabilities of contemporary SoC-FPGA platforms and comes with an ad-hoc scheduling infrastructure designed to guarantee bounded response times for DPR-enabled accelerated tasks. This paper presents Fred-Linux, the reference implementation of the FRED framework for GNU/Linux. Fred-Linux allows developing rich applications while leveraging predictable FPGA-based hardware acceleration for performing heavy computations. Fred-Linux has been developed using the Zynq-7000 and Zynq-UltraScale＋ by Xilinx as reference platforms, and it can be easily ported and extended on other platforms thanks to its modular design.

Process Variability Analysis in Interconnect, Logic, and Arithmetic Blocks of 16-nm FinFET FPGAs

In the current work, we study the process variability of logic, interconnect, and arithmetic/DSP resources in commercial 16-nm FPGAs. We create multiple, soft-macro sensors for each distinct resource under evaluation, and we deploy them across the FPGA fabric to measure intra-die variation, as well as across multiple FPGAs to measure inter-die variation. The derived results are used to create device-signature variability maps characterizing the distribution of variability across the die. Our study includes decoupling of variability to systematic and stochastic parts, exploration of variability under various voltage and temperature conditions and correlation analysis between the variability maps of the different resources. Furthermore, we scrutinize the impact of variability on the performance of actual test circuits and correlate the retrieved results with the sensor-based maps. Our experimental results on four Zynq XCZU7EV FPGAs showed significant intra- and inter-die variability, up to 7.8% and 8.9%, respectively, with a small increase under certain operating conditions. The correlation analysis demonstrated a strong correlation between the logic and arithmetic resources, whereas the interconnects showed a slightly weaker correlation in specific devices. Finally, a relatively moderate correlation was calculated between the variability maps and performance of test circuits due their dissimilar operating behavior versus our sensors.

Efficient heterogeneous matrix profile on a CPU + High Performance FPGA with integrated HBM

In this work, we study the problem of efficiently executing a state-of-the-art time series algorithm class – SCAMP – on a heterogeneous platform comprised of CPU + High Performance FPGA with integrated HBM (High Bandwidth Memory). The geometry of the algorithm (a triangular matrix walk) and the FPGA capabilities pose two challenges. First, several replicated IPs can be instantiated in the FPGA fabric, so load balance is an issue not only at system-level (CPU+FPGA), but also at device-level (FPGA IPs). And second, the data that each one of these IPs accesses must be carefully placed among the HBM banks in order to efficiently exploit the memory bandwidth offered by the banks while optimizing power consumption.To tackle the first challenge we propose a novel hierarchical scheduler named Fastfit, to efficiently balance the workload in the heterogeneous system while ensuring near-optimal throughput. Our scheduler consists of a two level scheduling engine: (1) the system-level scheduler, which leverages an analytical model of the FPGA pipeline IPs, to find the near-optimal FPGA chunk size that guarantees optimal FPGA throughput; and (2) a geometry-aware device-level scheduler, which is responsible for the effective partitioning of the FPGA chunk into sub-chunks assigned to each FPGA IP. To deal with the second challenge we propose a methodology based on a model of the HBM bandwidth usage that allows us to set the minimum number of active banks that ensure the maximum aggregated memory bandwidth for a given number of IPs. Through exhaustive evaluation we validate the accuracy of our models, the efficiency of our intra-device partition strategies and the performance and energy efficiency of our Fastfit heterogeneous scheduler, finding that it outperforms state-of-the-art previous schedulers by achieving up to 99.4% of ideal performance.

Improving the Quality of FPGA RO-PUF by Principal Component Analysis (PCA)

Ring Oscillator Physical Unclonable Functions (RO-PUFs) exploit the inherent manufacturing process variations, such as systematic and stochastic variations, to generate secret PUF responses that are unique to the device. Stochastic variations are random, while systematic variation exhibits a strong spatial correlation. Therefore, systematic process variation reduces the randomness of the PUF response. This lowers the ability of a PUF response to uniquely identify and authenticate individual devices. Further, the impact of systematic variation is paramount when the two ROs in comparison are placed far apart. Comparing the ROs that are close to each other does improve the randomness, but the responses generated are unreliable and limiting the possible Challenge-Response Pairs (CRPs). In this article, we are proposing a method to reduce the impact of systematic process variation on the RO oscillation frequencies by using Principal Component Analysis (PCA). Principal Components (PCs) model the directions of systematic and stochastic variation present on a device. By projecting the oscillation frequencies in the direction of stochastic variation, the impact of systematic variation can be reduced. Our proposed method neither restricts the placement of ROs to close groups nor limits the possible CRPs. The method is evaluated on a large population of 218 Xilinx Artix-7 FPGAs. To evaluate the efficiency of the proposed method, we purposely paired the ROs that are placed far apart on the FPGA fabric. Results obtained prove the ability of the proposed method in removing the impact of systematic variation on the oscillation frequencies and thereby producing truly random responses.

Fast and efficient FPGA implementation of Polar Codes and SoC test bench

In this paper we describe a novel and efficient System on Chip Field Programmable Gate Array (SoC FPGA) implementation and test bench for short Polar Codes on an Intel DE10-Standard Development Kit. Encoder and decoder are synthesized on the FPGA fabric and the whole functionality of a complete test bench is developed with an embedded ARM-based hard processor system. A Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) parametric design allows synthesis for different code lengths and is suitable for rate-adaptive decoding schemes. We implement fully-unrolled encoder and decoder architectures to achieve high troughputs and lower energy requirements, and achieve an 11% higher throughput than a reference implementation, for short Polar Codes. A novel Merged Processing Element (MPE) is optimized to be used with Sign–Magnitude LLR (SM LLR) discrete representations and pre-computing results in the decoder to reduce latency and resource consumption in comparison to reference designs. A simplified version of this MPE is also implemented, trading higher latencies for lower resource requirements. The SoC test bench design allows single-board automated testing and is also suitable for other error-correcting schemes. Error-correcting performance is evaluated for different combinations of integer and decimal part bits in LLR quantified representations. Also a new simplified non-statistical LLR metric was tested with promising results.

Design Automation for Tree-based Nearest Neighborhood–aware Placement of High-speed Cellular Automata on FPGA with Scan Path Insertion

Cellular Automata (CA) is attractive for high-speed VLSI implementation due to modularity, cascadability, and locality of interconnections confined to neighboring logic cells. However, this outcome is not easily transferable to tree-structured CA, since the neighbors having half and double the index value of the current CA cell under question can be sufficiently distanced apart on the FPGA floor. Challenges to meet throughput requirements, seamlessly translate algorithmic modifications for changing application specifications to gate level architectures and to address reliability challenges of semiconductor chips are ever increasing. Thus, a proper design framework assisting automation of synthesizable, delay-optimized VLSI architecture descriptions facilitating testability is desirable. In this article, we have automated the generation of hardware description of tree-structured CA that includes a built-in scan path realized with zero area and delay overhead. The scan path facilitates seeding the CA, state modification, and fault localization on the FPGA fabric. Three placement algorithms were proposed to ensure maximum physical adjacency amongst neighboring CA cells, arranged in a multi-columnar fashion on the FPGA grid. Our proposed architectures outperform implementations arising out of standard placers and behavioral designs, existing tree mapping strategies, and state-of-the-art FPGA centric error detection architectures in area and speed.

AN EFFICIENT FPGA OVERLAY FOR COLOR TRANSFORMATION FUNCTION USING HIGH LEVEL SYNTHESIS

Image Processing is a significantly desirable in commercial, industrial, and medical applications. Processor based architectures are inappropriate for real time applications as Image processing algorithms are quite intensive in terms of computations. To reduce latency and limitation in performance due to limited amount of memory and fixed clock frequency for synthesis in processor-based architecture, FPGA can be used in smart devices for implementing real time image processing applications. To increase speed of real time image processing custom overlays (Hardware Library of programmable logic circuit) can be designed to run on FPGA fabric. The IP core generated by the HLS (High Level Synthesis) can be implemented on a reconfigurable platform which allows effective utilization of channel bandwidth and storage. In this paper we have presented FPGA overlay design for color transformation function using Xilinx’s python productivity board PYNQ-Z2 to get benefit in performance over a traditional processor. Performance comparison of custom overlay on FPGA and Processor based platform shows FPGA execution yields minimum computation time.

An Application Specific Reconfigurable Architecture with Reduced Area and Static Memory Cells

An Application Specific Inflexible FPGA (ASIF) is a tailored design, for a given group of known circuits, which is generated by extensively reducing the routing resources of an FPGA. In an ASIF, different dynamically reconfigurable application circuits are initially mapped and tested on an FPGA fabric. Subsequently, the FPGA fabric is reduced to achieve an efficient architecture for known application circuits. However, a large portion of ASIF is still occupied by fully flexible logic blocks, containing the same amount of area and SRAM memory cells, as found in a traditional FPGA. Thus, here lies a potential to further optimize the logic blocks of an ASIF at the expense of removing or reducing their reconfigurability. This work optimizes the logic blocks of an ASIF through the SRAM-Table sharing technique, without compromising their reconfigurability. Moreover, the routing channels of ASIF are further optimized by applying the Boolean functions (Gates) insertion technique. The applied techniques (SRAM-Table sharing and Boolean functions insertion) not only reduce the area, delay and power, but also minimize the reconfiguration time, bitstream size and the size of external memory required to store the bitstream of circuits. This optimized version of ASIF is termed as ASIF[Formula: see text]. Furthermore, an embedded FPGA in a System-on-Chip that requires the partial dynamic reconfiguration for known circuits, can be automatically reduced to an ASIF[Formula: see text]. It is found through experimental results that an ASIF[Formula: see text] is 4–9[Formula: see text] area-efficient and requires [Formula: see text] lesser number of SRAM cells, as compared to the previously proposed ASIF for a group of 2–5 circuits. It also achieves 34–53[Formula: see text] area saving as compared to a traditional FPGA.

An OpenGL Compliant Hardware Implementation of a Graphic Processing Unit Using Field Programmable Gate Array–System on Chip Technology

FPGA-SoC technology provides a heterogeneous platform for advanced, high-performance systems. The System on Chip (SoC) architecture combines traditional single and multiple core processor topologies with flexible FPGA fabric. Dynamic reconfiguration allows the hardware accelerators to be changed at run-time. This article presents a novel OpenGL compliant GPU design implemented on an FPGA. The design uses an FPGA-SoC environment allowing the embedded processor to offload graphics operation onto a more suitable architecture. To the authors’ knowledge, this is a first. The graphics processor consists of GLSL compliant shaders, an efficient Barycentric Rasterizer, and a draw mode manager. Performance analysis shows the throughput of the shaders to be hundreds of millions of vertices per second. The design uses both pipelining and resource reuse to optimise throughput and resource use, allowing implementation on a low-cost, FPGA device. Pixel processing rates from this implementation are almost 80% higher than other FPGA implementations. Power consumption compared with comparative embedded devices shows the FPGA consuming as little as 2% of the power of a Mali device, and an up to 11.9-fold increase in efficiency compared to an Nvidia RTX 2060 - Turing architecture device.

Comparative Analysis of Processor-FPGA Communication Performance in Low-Cost FPSoCs

Field-programmable system-on-chip (FPSoC) devices, combining high-performance processors and FPGA fabric in the same chip, are currently a leading technology in the design of complex digital systems. Since design times are longer than those of systems based on graphic processing units or standalone processors, many efforts are being devoted to develope efficient compilers from high-level languages. Even though, efficient processor-FPGA communication is still an important open issue. To contribute to this area, this article presents an extensive characterization of the processor-FPGA communication delays in Zynq-7000 devices. Although partial analyses of communication performance in these devices have been reported, this is the first work to address very important issues such as the use of DMA for data transfers or the effect of L2 cache controller settings and external RAM controller settings. As a result, data transfer rates are analyzed considering all parameters that influence them. The performance of Zynq-7000 devices is also compared to that of Cyclone V devices, hence covering the two most important current families that dominate the FPSoC market. This information is of utmost importance for designers to optimize processor-FPGA communication and, in turn, the performance of their FPSoC-based systems.

Efficient FPSoC Prototyping of FCS-MPC for Three-Phase Voltage Source Inverters

This work describes an efficient implementation in terms of computation time and resource usage in a Field-Programmable System-On-Chip (FPSoC) of a Finite Control Set Model Predictive Control (FCS-MPC) algorithm. As an example, the FCS-MPC implementation is used for the current reference tracking of a two-level three-phase power converter. The proposed solution is an enabler for using both complex control algorithms and digital controllers for high switching frequency semiconductor technologies. An original HW/SW (hardware and software) system architecture for an FPSoC is designed to take advantage of a modern operating system, while removing time uncertainty in real-time software tasks, and exploiting dedicated FPGA fabric for the most complex computations. In addition, two different architectures for the FPGA-implemented functionality are proposed and compared in order to study the area-speed trade-off. Experimental results show the feasibility of the proposed implementation, which achieves a speed hundreds of times faster than the conventional Digital Signal Processor (DSP)-based control platform.