FPGA-based Simulator Research Articles

Implementation of Artificial Neural Networks on Field-Programmable Gate Arrays

Implementing Artificial Neural Networks (ANNs) on Field-Programmable Gate Arrays (FPGAs) provides a promising solution for achieving high-performance, low-latency, and energy-efficient computations in complex tasks. This paper investigates the methodology for mapping ANNs onto FPGAs, focusing on critical aspects such as architecture selection, hardware design, and optimization techniques. By harnessing the parallel processing capabilities and reconfigurability of FPGAs, neural network computations are significantly accelerated, making them ideal for real-time applications like image processing and embedded systems. The implementation process addresses key considerations, including fixed-point arithmetic, memory management, and dataflow optimization, while employing advanced techniques such as pipelining, quantization, and pruning. The research compares the accuracy and performance speedup of ANNs on CPUs versus FPGAs, revealing that FPGA-based simulations are 4680 times faster than CPU-based simulations using MATLAB, without compromising prediction accuracy.

Real-Time Digital Simulator Design for Differential Drive Mobile Robot using FPGA

This paper presents a real-time simulation of a differential drive mobile robot (DDMR). The permanent magnet DC motors that drive the robot’s left and right wheels were modeled and executed in real-time on a Field Programmable Gate Array (FPGA) based co-simulator platform, interfacing with the Webots robot simulator, which simulates the DDMR on the PC side. The electrical parameters, which are not available in robot simulators, were simulated and measured by the proposed co-simulator system in real-time under various environmental conditions and trajectories of the robot. Parameters such as current, voltage, and torque were measured instantaneously, enabling a more realistic simulation. Additionally, the cycle time of the robot simulator was determined to be 32 ms, and the developed FPGA-based simulation operated at approximately 2000 times the speed of the robot simulator. The results demonstrate the applicability of the developed platform in robotic applications.

A Model of Thermally Activated Molecular Transport: Implementation in a Massive FPGA Cluster

In this paper, a massively parallel implementation of Boltzmann’s thermally activated molecular transport model is presented. This models allows taking into account potential energy barriers in molecular simulations and thus modeling thermally activated diffusion processes in liquids. The model is implemented as an extension to the basic Dynamic Lattice Liquid (DLL) algorithm on ARUZ, a massively parallel FPGA-based simulator located at BioNanoPark Lodz. The advantage of this approach is that it does not use any exponentiation operations, minimizing resource usage and allowing one to perform simulations containing up to 4,608,000 nodes.

Methods for the Accurate Real-Time Simulation of High-Frequency Power Converters

This article presents general modeling approaches to achieve an accurate real-time simulation (RTS) of high switching frequency converters.The proposed methods are based on the direct mapped method (DMM) and make use of decoupling techniques when appropriate. The DMM links state variables to diode statuses and provides an exact and noniterative solution to network equations. An electric vehicle battery charger test case comprised of a full-bridge rectifier, an interleaved boost, and a three-phase <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LLC</i> is used to demonstrate the high accuracy achieved by the proposed methods compared to a conventional approach. Field-programmable gate array (FPGA) implementations are proposed and shown to achieve from 75- to 175-ns RTS time steps for this test case circuit, allowing its accurate simulation while switched at 200 kHz. To further validate the effectiveness of the FPGA-based simulator, a resonant boost converter is also implemented and simulated in real time.

High performance computing engines for the FPGA-based simulation of the ULM

This paper presents a design methodology for the FPGA-based simulation of the Universal Line Model (ULM). The proposed approach yields a higher computational performance compared to alternative implementations reported in the literature. Such performance allows the use of the FPGA model in real-time simulation applications or for the acceleration of offline EMT programs. A state-space approach is used to perform the time-domain simulation of the pole-residue form of the rational fitting of the characteristic admittance and propagation functions. The paper also discusses the appropriate scheduling of the ULM computations and proper management of the history terms that lead to an optimized hardware utilization, low latency response times, and higher computational performances using floating-point arithmetic.

FPGA‐based hardware‐in‐the‐loop real‐time simulation implementation for high‐speed train electrical traction system

The hardware-in-the-loop (HIL) real-time simulation for high-speed train electrical traction system aims to reduce the design cost and speed up control verification process of algorithms in the developmental stage of the traction control unit. In this study, based on the dSPACE real-time simulator, the multiple-simulator, multiple-simulation step of HIL real-time simulation system is first built. Second, for the associated discrete circuit modelling method, an optimisation method is proposed to minimise the switching loss and improve the simulation accuracy by selecting the optimal discrete-time switch admittance parameter, G S . To decrease the computational burden for field-programmable gate array (FPGA), a decoupling method without simulation latency is presented to reduce the matrix dimension of the system model. Finally, the real-time simulation models of electrical traction system are realised by CPU + FPGA-based simulator, in which the power electronics converter models are computed in FPGA with a fixed 100 ns time-step. The validity and reliability of the real-time simulation system is verified by the HIL simulation and experimental results, which indicate that the real-time HIL simulation at the nanosecond level improves the accuracy essentially.

Synthesis and Analysis of the Fixed-Point Hodgkin–Huxley Neuron Model

In many tasks related to realistic neurons and neural network simulation, the performance of desktop computers is nowhere near enough. To overcome this obstacle, researchers are developing FPGA-based simulators that naturally use fixed-point arithmetic. In these implementations, little attention is usually paid to the choice of numerical method for the discretization of the continuous neuron model. In our study, the implementation accuracy of a neuron described by simplified Hodgkin–Huxley equations in fixed-point arithmetic is under investigation. The principle of constructing a fixed-point neuron model with various numerical methods is described. Interspike diagrams and refractory period analysis are used for the experimental study of the synthesized discrete maps of the simplified Hodgkin–Huxley neuron model. We show that the explicit midpoint method is much better suited to simulate the neuron dynamics on an FPGA than the explicit Euler method which is in common use.

FlexHH: A Flexible Hardware Library for Hodgkin-Huxley-Based Neural Simulations

The Hodgkin-Huxley (HH) neuron is one of the most biophysically-meaningful models used in computational neuroscience today. Ironically, the model's high experimental value is offset by its disproportional computational complexity. To such an extent that neuroscientists have either resorted to simpler models, losing precious neuron detail, or to using high-performance computing systems, to gain acceleration, for complex models. However, multicore/multinode CPU-based systems have proven too slow while FPGA-based ones have proven too time-consuming to (re)deploy to. Clearly, a solution that bridges user friendliness and high speedups is necessary. This paper presents flexHH, a flexible FPGA library implementing five popular, highly parameterizable variants of the HH neuron model. flexHH is the first crucial step towards making FPGA-based simulations of compute-intensive neural models available to neuroscientists without the debilitating penalty of re-engineering and re-synthesis. Through flexHH, the user can instantiate custom models and immediately take advantage of the acceleration without the mediation of an engineer, which has proven to be a major inhibitor to full adoption of FPGAs in neuroscience labs. In terms of performance, flexHH achieves speedups between $8\times $ -$20\times $ compared to sequential-C implementations, while only a small drop in real-time capabilities is observed when compared to hardcoded FPGA-based versions of the models tested.

Device‐level modelling and FPGA‐based real‐time simulation of the power electronic system in fuel cell electric vehicle

Power electronic converters are essential components in the fuel cell electric vehicle (FCEV) powertrain, which precisely control the power output of the fuel cell stack, the charging and discharging process of the battery, and the operation of the traction motor. The hardware-in-the-loop (HIL) simulation plays an important role in the rapid validation of power converters in their early development stages. In this study, a device-level model of the power converters in FCEV powertrain is developed for the FPGA-based real-time simulation. By fulfilling the circuit topology partitioning and the switch model partitioning, the FCEV power electronic system can be simulated with sub-microsecond time-step while producing the detailed switching waveforms with 5 ns resolution. Therefore, the device electrical stress, and the switching power losses can be evaluated in real time. Furthermore, the electro-thermal converter model is developed accordingly, which makes it possible to evaluate the IGBT/Diode thermal behaviour in the HIL simulation. In this study, the FPGA hardware is designed with the NI LABVIEW FPGA module and implemented on the NI-7975R FLEXRIO FPGA board. The accuracy of the FPGA-based simulation results is evaluated by the results from offline simulation tools. The effectiveness of the proposed model is then validated by the controller HIL experiments.

A Device-Level Transient Modeling Approach for the FPGA-Based Real-Time Simulation of Power Converters

The device-level real-time simulation of power converters is constrained by the contradiction between the required short simulation time step to describe the transient behaviors and the large computational amount caused by the nonlinearities of switches’ models. In this paper, a novel low-latency device-level power converter modeling approach is proposed for field programmable gate array (FPGA)-based real-time simulation. A piecewise linear insulated-gate bipolar transistor (IGBT)/diode transient model is proposed based on the inductive switching behaviors. The switching transient is modeled into four phases, which are identified by the boundaries between three operating regions of IGBT and between two operating modes of a diode. Moreover, each phase is approximated by a linear continuous behavior in order to reduce the real-time computational amounts. Accompanied by the effective boundary identification, the device-level IGBT/diode model can be efficiently integrated into the real-time simulation with low computational latency. A dc–dc–ac topology model is implemented on the FPGA-based real-time platform, as a case study to verify the effectiveness and practicability of the proposed approach. With the help of circuit partitioning techniques, the device-level converter model can be simulated with a 50-ns time step on FPGA. Moreover, the accuracy of FPGA-based simulation results is validated by the error evaluation with respect to the results from offline simulation tools.

Exploration of FPGA‐based electromagnetic transient real‐time simulation system design using high‐level synthesis

Field-programmable gate array (FPGA)-based simulation system is applied in real-time electromagnetic transient (EMT) simulation for small time-step simulation. However, the FPGA-based simulation system requires handcrafted hardware description language (HDL) and significant design efforts. This paper explores FPGA-based EMT real-time simulation system design using high-level synthesis (HLS) technology to accelerate the design process and improve the flexibility, because high-level language can be transferred into HDL using HLS. Furthermore, loop unroll and pipeline optimisation directives are analysed and applied for HLS to improve the computation speed of the components. The system can simulate various components, including switches, R-L-C, voltage sources, current sources, and transmission lines. Especially, the system adopting double-precision floating-point calculation can support the network with 74 nodes and achieve 2 us for each small time step on Xilinx Virtex7-690 T FPGA. Comparison of simulation results from offline simulation tools with those from the proposed simulation system validates the correctness of the FPGA-based EMT simulation system using HLS technology.

FPGA-based hardware simulation of nonlinear autoregressive Volterra model to reconstruct the single neuron spike pattern

This study explores the implementation of the nonlinear autoregressive Volterra (NARV) model using a field programmable gate arrays (FPGAs)-based hardware simulation platform and accomplishes the identification process of the Hodgkin–Huxley (HH) model. First, a physiological detailed single-compartment HH model is applied to generate experiment data sets and the electrical behavior of neurons are described by the membrane potential. Then, based on the injected input current and the output membrane potential, a second-order NARV model is constructed and implemented on FPGA-based simulation platforms. The NARV modeling method is data-driven, requiring no accurate physiological information and the FPGA-based hardware simulation can provide a real time and high-performance platform to deal with the drawbacks of software simulation. Therefore, the proposed method in this paper is capable of handling the nonlinearities and uncertainties in nonlinear neural systems and may help promote the development of clinical treatment devices.

A Very Fast Trace-Driven Simulation Platform for Chip-Multiprocessors Architectural Explorations

Simulation is the main tool for computer architects and parallel application developers for developing new architectures and parallel algorithms on many-core machines. Simulating a many-core architecture represent a challenge to software simulators even with parallelization of these SW on multi-cores. Field Programmable Gate Arrays offer an excellent implementation platform due to inherent parallelism. Existing FPGA-based simulators however, are mostly execution-driven which consumes too many FPGA resources. Hence, they still trade-off accuracy with simulation speed as SW simulators do. In this work, an application-level trace-driven FPGA-based many-core simulator is presented. A parameterized Verilog template was developed that can generate any number of simulator tiles. The input trace has an architecturally agnostic format that is directly interpreted by the FPGA-based timing model to re-construct the execution events of the original application with accurate timing. This allows fitting a large number of simulation tiles on a single FPGA without sacrificing simulation speed or accuracy. Experimental results show that the simulator's average accuracy is ∼14 percent with simulation speeds ranging from 100’s of MIPs to over 2,200 MIPS for a 16-core target architecture. Hence, with accuracy similar to SW simulators, its speed is higher than all other FPGA-based simulators.

FPGA-Based Image Pre-Processor Design and Simulation

FPGA-Based Image Pre-Processor Design and Simulation

Real-time simulation of dynamic vehicle models using a high-performance reconfigurable platform

With the increase in the complexity of models and lack of flexibility offered by the analog computers, coupled with the advancements in digital hardware, the simulation industry has subsequently moved to digital computers and increased usage of programming languages such as C, C++, and MATLAB. However, the reduced time-step required to simulate complex and fast systems imposes a tighter constraint on the time within which the computations have to be performed. The sequential execution of these computations fails to cope with the real-time constraints which further restrict the usefulness of Real-Time Simulation (RTS) in a Virtual Reality (VR) environment. In this paper, we present a methodology for the design and implementation of RTS algorithms, based on the use of Field-Programmable Gate Array (FPGA) technology. We apply our methodology to an 8th order steering valve subsystem of a vehicle with relatively low response time requirements and use the FPGA technology to improve the response time of this model. Our methodology utilizes traditional hardware/software co-design approaches to generate a heterogeneous architecture for an FPGA-based simulator by porting the computationally complex regions to hardware. The hardware design was optimized such that it efficiently utilizes the parallel nature of FPGAs and pipelines the independent operations. Further enhancement was made by building a hardware component library of custom accelerators for common non-linear functions. The library also stores the information about resource utilization, cycle count, and the relative error with different bit-width combinations for these components, which is further used to evaluate different partitioning approaches. In this paper, we illustrate the partitioning of a hardware-based simulator design across dual FPGAs, initiate RTS using a system input from a Hardware-in-the-Loop (HIL) framework, and use these simulation results from our FPGA-based platform to perform response analysis. The total simulation time, which includes the time required to receive the system input over a socket (without HIL), software initialization, hardware computation, and transfer of simulation results back over a socket, shows a speedup of 2 × as compared to a similar setup with no hardware acceleration. The correctness of the simulation output from the hardware has also been validated with the simulated results from the software-only design.

Bearing Performance Degradation Signal Simulation Based on Health Confidence Value Injection and FPGA

A digital simulation method for the performance degradation signal of rolling bearings is developed based on the analysis of experimental data. A self-organizing map neural network is utilized to build the performance degradation assessment model of the rolling bearings based on characteristic parameter extraction. Wavelet packet decomposition is then implemented to extract the wavelet coefficients in the corresponding performance degradation sensitive band. Different health confidence values are injected into the extracted wavelet packet coefficients, and signals are reconstructed according to the simulation needs to obtain rolling bearing vibration data under different degradation degrees. Understanding the exact mathematical model of the measured object is unnecessary in this method; the method is simple and reliable and helps solve the problem of performance degradation data simulation. Finally, an FPGA-based performance degradation signal simulator is designed by combining the analogy procedure, employed to support the verification process of fault diagnosis and prediction capability.

An FPGA-Based Transient Error Simulator for Resilient Circuit and System Design and Evaluation

Error detection and correction (EDAC) has become more important with continued device scaling. We propose a field-programmable gate array (FPGA)-based simulator to accelerate the transient simulation of pipeline-level EDAC circuits and their interactions with circuits under test (CUTs). The simulator incorporates the CUT delay profile, the CUT error profile, and the EDAC model. The FPGA-based simulator captures the fine-grained interactions between the CUT and EDAC for the evaluation of the effectiveness of EDAC and its tuning. The simulator is constructed based on parameterized models, making it general purpose and widely applicable. We demonstrate the capability of this simulator in the evaluation of two popular pipeline-level EDAC designs, i.e., preedge EDAC and postedge EDAC, using synthesized processors that operate under generic error and noise models. The proposed error simulator uncovers key insights to help guide EDAC designs.

Spatially Coupled Soft-Decision Error Correction for Future Lightwave Systems

In this paper, we discuss and present some recent advances in the field of error correcting codes and discuss their applicability for lightwave transmission systems. We introduce several classes of spatially coupled codes and discuss several design options for spatially coupled codes and show how rapidly decodable codes can be constructed by careful selection of the degree distribution. We confirm the good performance of some spatially coupled codes at very low bit error rates using an FPGA-based simulation. Finally, we compare all proposed schemes and show how spatially coupled Low-Density Parity-Check (LDPC) codes outperform conventional LDPC and polar codes with similar receiver complexity and memory requirements.

FPGA-Accelerated Simulation of Computer Systems

To date, the most common form of simulators of computer systems are software-based running on standard computers. One promising approach to improve simulation performance is to apply hardware, specifically reconfigurable hardware in the form of field programmable gate arrays (FPGAs). This manuscript describes various approaches of using FPGAs to accelerate software-implemented simulation of computer systems and selected simulators that incorporate those techniques. More precisely, we describe a simulation architecture taxonomy that incorporates a simulation architecture specifically designed for FPGA accelerated simulation, survey the state-of-the-art in FPGA-accelerated simulation, and describe in detail selected instances of the described techniques. Table of Contents: Preface / Acknowledgments / Introduction / Simulator Background / Accelerating Computer System Simulators with FPGAs / Simulation Virtualization / Categorizing FPGA-based Simulators / Conclusion / Bibliography / Authors' Biographies

FPGA-Based Realization and Simulation of Channel De-Interleaving in TD-LTE System

This paper is based on the FPGA-based realization of Channel De-interleaving in LTE system, including simulation, synthesis and board-level verification on the Virtex-6 chip. Implementation results show that, the encoding and decoding algorithm applied to the TD-LTE RF conformance testing instrument has advantages of high efficiency and good reliability.