FPGA-based Signal Processing Research Articles

An Integrated Primary Impulse Radio Ultra-Wideband Radar for Short-Range Real-Time Localization

This paper presents a primary impulse-radio ultra-wideband (IR-UWB) radar system for real-time short-range localization, e.g., for smart traffic and automotive applications. The radar system consisting of an integrated radar transceiver (TRx) using 45-nm SOI CMOS technology and an FPGA-based signal processing. The efficient transmitter (Tx), which complies with the regulations for both indoor and outdoor applications, modulates and emits a seventh derivative Gaussian pulse. In the receiver (Rx), echo signals will be amplified and sampled in real-time. The echo pulses are recovered by signal processing hardware on the FPGA, which is also used to perform simple classification tasks like user warning. The radar system is compact, portable, and power efficient. The Tx has a high-energy efficiency of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathrm {11~ \text {p} \text {J} /pulse}$ </tex-math></inline-formula> . The proposed radar system achieves very high signal-to-noise ratio (SNR) and range precision. It has a maximum detection range of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathrm {15~m }$ </tex-math></inline-formula> and a range resolution down to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathrm {3~ \text {cm}}$ </tex-math></inline-formula> . Moreover, a target of interest can be warned with a latency as fast as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathrm {16~\mu s }$ </tex-math></inline-formula> by using 1-bit real-time sampling.

Self-correction of air refractive index in distance measurement using two-color sinusoidal phase modulating interferometry

A two-color sinusoidal phase modulating (SPM) interferometer based on electro-optic modulator (EOM) is devised for self-correction of air refractive index in distance measurement. Two laser sources with high frequency stability and close wavelengths (633 nm and 782 nm) are used in this scheme. High-accuracy phase demodulation was realized using phase generated carrier (PGC) demodulation techniques with an FPGA-based signal processing board. Experimental results of nanometer displacement measurements show that the resolution and accuracy of PGC demodulation is better than 1°, and the nonlinear error is less than 0.2°. Performance tests of two-color SPM interferometer compared with one-color interferometers under dynamic environment were implemented with an arm length difference of 4 m. The results show that, the measured distance of one-color interferometer drifts 4.8 μm in 600 s, which is caused by the deviation between the measured value of air refractive index and the actual value along the laser propagation path, and this drift reduces to ±1.5 μm using two-color interferometer without environmental sensing.

Real-time FPGA-based signal processing for silicon-on-insulator MOSFET single-photon detector: study on photon number statistics

In this paper, the real-time signal processing for the silicon-on-insulator MOSFET single-photon detector is investigated. The output waveforms of the detector consist of rising and falling edges that correspond to hole generation by the photon incidence and spontaneous hole recombination, respectively, and current levels related to the number of stored holes. The signal processor has been developed to detect the rising edge and measure the step height that represents the number of photogenerated holes at the same time and implemented to a field programmable gate array for real-time processing. In order to verify its operation, waveforms at different light intensities are processed, and it is successfully demonstrated that the statistical distribution of generated holes in a unit observation time follows the Poisson distribution.

Design of a 128‐channel transceiver hardware for medical ultrasound imaging systems

In this work, the design and development of a 128-channel transceiver hardware for medical ultrasound imaging systems and research is presented. The proposed hardware solution integrates the analog front-end (AFE) sections, high voltage transmit pulser sections, field programmable gate array (FPGA)-based transmit beamforming and control logic, time gain compensation (TGC) and continuous (CW) Doppler functional circuits, and the necessary power supplies (high voltage (HV) and low voltage (LV)) into a single board. In addition, it integrates pervasive segments like power, clock tree sections, and power management and debugger logic. The developed transceiver solution helps to advance the research in medical ultrasound imaging techniques and technologies. To prototype an ultrasound imaging system, the developed hardware can be interfaced with a 128-channel ultrasound transducer array and an FPGA-based signal processing module. As the transceiver hardware is designed with commercially available chipsets, it provides the flexibility to programme the ultrasound AFE signal chain, transmit beamforming and the arbitrary transmit wave pattern. Besides, compared to the commercial open ultrasound research scanners, the flexibility to interface FPGA-based signal processing module helps to investigate the performance of hardware realisation of various ultrasound signal processing algorithms. Moreover, the work realises a single-board transceiver solution for multichannel ultrasound system fulfilment.

Design of FPGA-based Signal Processing of EWRG for Localized Heavy Rainfall Observation

Design of FPGA-based Signal Processing of EWRG for Localized Heavy Rainfall Observation

Simple and low-cost tabletop NMR system for chemical-shift-resolution spectra measurements

We have been working on developing a low-cost tabletop NMR system. We reported that a field homogeneity as high as 50 ppm was achieved with a simple NMR magnet by employing two facing ferrite magnets with iron disks in between (Chonlathep et al., 2017). In this paper, we report two improvements added to our previous system: (1) an FPGA based signal processing unit to improve the S/N ratio and (2) a simple shimming mechanism to improve the field homogeneity. We obtained as high as 1 ppm field homogeneity in the best case. The signals from hydrogen nuclear spins in a methyl and carboxy group in acetic acid were resolved in NMR spectra.

Efficient FPGA-based FIR – architecture and its significance in ultrasonic signal processing

The presented work demonstrates the most suitable architecture for the FPGA-based signal processing which makes available various real-time filtering algorithms, such as band pass, high pass, low pass, and band-reject for FIR filters. The processor was implemented with the fixed-point arithmetic using VHDL, which can be downloadable on FPGA device. The FPGA device can be interfaced with an analog-to-digital converter (ADC), digital-to-analog converter (DAC) and a personal computer with MATLAB for the user interface and feeding coefficients and order of the filter. The core part of this paper was to find the reconfigurable and efficient architecture of the processor with only one multiplier which can work for Finite Impulse response (FIR) filter with the best- suited structure. The system will be used for automatic generation of fixed-point FIR filters. The model was also implemented in MATLAB script and the verification of results in the case of low-pass filtering confirmed that both models in MATLAB and VHDL matched to each other. All components of architecture in VHDL were designed using generics which allow changing its structure and behavior by generic values. Therefore, it is a universal filter platform where user can process the data while changing the filter parameters as per the requirement of applications. The complete design was verified by taking the example of audio signal frequency, but parameterized components of system architecture can also facilitate its applicability at ultrasonic frequencies by changing the algorithm. The significance and applicability of FPGAs in ultrasonic signal processing were also studied and reviewed.

High-dynamic-range arrival time control for flexible, accurate and precise parametric sub-cycle waveform synthesis.

We introduce a simple all-inline variation of a balanced optical cross-correlator (BOC) that allows to measure the arrival time difference (ATD), over the full Nyquist bandwidth, with increased common-mode rejection and long-term stability. An FPGA-based signal processing unit allows for real-time signal normalization and enables locking to any setpoint with an unprecedented accuracy of 0.07 % within an increased ATD range of more than 400 fs, resulting in attosecond resolution locking. The setup precision is verified with an out-of-loop measurement to be less than 80 as residual jitter paving the way for highly demanding applications such as parametric waveform synthesizers.

HIPSR: A Digital Signal Processor for the Parkes 21-cm Multibeam Receiver

HIPSR (HI-Pulsar) is a digital signal processing system for the Parkes 21-cm Multibeam Receiver that provides larger instantaneous bandwidth, increased dynamic range, and more signal processing power than the previous systems in use at Parkes. The additional computational capacity enables finer spectral resolution in wideband HI observations and real-time detection of Fast Radio Bursts during pulsar surveys. HIPSR uses a heterogeneous architecture, consisting of FPGA-based signal processing boards connected via high-speed Ethernet to high performance compute nodes. Low-level signal processing is conducted on the FPGA-based boards, and more complex signal processing routines are conducted on the GPU-based compute nodes. The development of HIPSR was driven by two main science goals: to provide large bandwidth, high-resolution spectra suitable for 21-cm stacking and intensity mapping experiments; and to upgrade the Berkeley–Parkes–Swinburne Recorder (BPSR), the signal processing system used for the High Time Resolution Universe (HTRU) Survey and the Survey for Pulsars and Extragalactic Radio Bursts (SUPERB).

Ultrasound flow mapping of complex liquid metal flows with spatial self-calibration

Investigating the complex interaction of electrically conductive fluids and magnetic fields is relevant for a variety of applications from basic research in magnetohydrodynamics (MHD) to modeling of industrial processes involving metal melts, such as steel casting and crystal growth. However, experimental studies in this field are often limited by the performance of flow instrumentation for opaque liquids. Commercially available measurement systems usually lack the ability to provide a time-resolved imaging of transient flow structures. We present an ultrasound array Doppler velocimeter (UADV) for flow mapping in opaque liquids near room temperature. It is modular and flexible regarding its measurement configuration, for instance it allows capturing two velocity components in two planes (2d–2c) of 67×67mm2 with a frame rate of 30Hz. It uses up to 9 linear arrays with 25 ultrasound transducers each driven in a parallelized time division multiplex (TDM) scheme. A FPGA-based signal processing allows a continuous realtime operation of the measurement system. Combining the single-component velocity data of each linear array to a 2d–2c flow field demands precise knowledge of the relative geometric position of the transducer arrays. We present a novel method that performs a spatial self-calibration by a mutual time of flight measurement, significantly reducing alignment errors. A measurement example of a magnetically stirred flow of GaInSn in a rectangular container is given. The UADV is applied to experiments in the context of manufacturing crystalline silicon ingots for photovoltaics.

Modular Ultrasound Array Doppler Velocimeter with FPGA-based Signal Processing for Real-time Flow Mapping in Liquid Metal

Investigating the complex interaction of conductive fluids and magnetic fields is relevant for a variety of applications from basic research in magnetohydrodynamics (MHD) to modeling industrial processes involving metal melts, such as the crystal growth process in the photovoltaic industry. This enables targeted optimizations of the melt flow and allows to significantly increase the yield and energy efficiency of industrial processes. However, experimental studies in this field are often limited by the performance of flow instrumentation for opaque liquids. We present an ultrasound array Doppler velocimeter (UADV) for flow mapping in opaque liquids at room temperature. It is modular and flexible regarding its measurement configuration, for instance it allows capturing two velocity components in two planes (2d − 2c). It uses up to 9 linear arrays with a total element count of 225, driven in a parallelized time division multiplex (TDM) scheme. A FPGA-based signal pre-processing allows to handle the massive data bandwidth of typ. 1.2 GB/s and enables a continuous and near-realtime operation of the measurement system. The capabilities of the UADV system are demonstrated in a basic MHD research experiment with a metal melt (GaInSn) in a cubic container of (67mm)3. The flow induced by a rotating magnetic field is captured with a temporal resolution of 250ms for the horizontal and vertical central cross-section of the cube.

An FPGA-Based Brain-Computer Interface for Wireless Electric Wheelchairs

A wireless EEG-based brain-computer interface (BCI) and an FPGA-based system to control electric wheelchairs through a Bluetooth interface was proposed in this paper for paralyzed patients. Paralytic patients can not move freely and only use wheelchairs in their daily life. Especially, people getting motor neuron disease (MND) can only use their eyes and brain to exercise their willpower. Therefore, real-time EEG and winking signals can help these patients effectively. However, current BCI systems are usually complex and have to send the brain waves to a personal computer or a single-chip microcontroller to process the EEG signals. In this paper, a simple BCI system with two channels and an FPGA-based circuit for controlling DC motor can help paralytic patients easily to drive the electric wheelchair. The proposed BCI system consists of a wireless physiological with two-channel acquisition module and an FPGA-based signal processing unit. Here, the physiological signal acquisition module and signal processing unit were designed for extracting EEG and winking signals from brain waves which can directly transformed into control signals to drive the electric wheelchairs. The advantages of the proposed BCI system are low power consumption and compact size so that the system can be suitable for the paralytic patients. The experimental results showed feasible action for the proposed BCI system and drive circuit with a practical operating in electric wheelchair applications.

Design and Implementation of FPGA Based Signal Processing Card

This paper describes the design of FPGA based signal processing card. An on board real time digital signal processing system is designed using FPGA. The platform can decode process of various kinds of digital and analog signals simultaneously. The design trend in this card is towards small size, high integration and fast real time processing. For the optimum performance a 16 bit 1 MSPS ADC is used which is interfaced with FPGA to make all the data processing onboard in real time. This card can be used in many signal processing based applications like audio signal processing, audio compression, digital image processing, video compression, speech processing, speech recognition, digital communications by interfacing several separate board using inbuilt I/O’s, each with a number of input channels that will communicate with each other in real time over a high speed communication link. The resulting images can be displayed directly on LCD or OLED panel displays using I/O’s peripherals. The project introduces many challenging issues, which are being addressed in turn with different prototype designs. These issues are the ADC performance, interfacing the ADCs to the FPGA, implementing the flexible processing algorithms and high speed interconnection between the boards.

Design and Implementation of FPGA Based Signal Processing Card

Design and Implementation of FPGA Based Signal Processing Card

Free-running ADC- and FPGA-based signal processing method for brain PET using GAPD arrays

Currently, for most photomultiplier tube (PMT)-based PET systems, constant fraction discriminators (CFD) and time to digital converters (TDC) have been employed to detect gamma ray signal arrival time, whereas anger logic circuits and peak detection analog-to-digital converters (ADCs) have been implemented to acquire position and energy information of detected events. As compared to PMT the Geiger-mode avalanche photodiodes (GAPDs) have a variety of advantages, such as compactness, low bias voltage requirement and MRI compatibility. Furthermore, the individual read-out method using a GAPD array coupled 1:1 with an array scintillator can provide better image uniformity than can be achieved using PMT and anger logic circuits. Recently, a brain PET using 72 GAPD arrays (4×4 array, pixel size: 3 mm×3 mm) coupled 1:1 with LYSO scintillators (4×4 array, pixel size: 3 mm×3 mm×20 mm) has been developed for simultaneous PET/MRI imaging in our laboratory. Eighteen 64:1 position decoder circuits (PDCs) were used to reduce GAPD channel number and three off-the-shelf free-running ADC and field programmable gate array (FPGA) combined data acquisition (DAQ) cards were used for data acquisition and processing. In this study, a free-running ADC- and FPGA-based signal processing method was developed for the detection of gamma ray signal arrival time, energy and position information all together for each GAPD channel. For the method developed herein, three DAQ cards continuously acquired 18 channels of pre-amplified analog gamma ray signals and 108-bit digital addresses from 18 PDCs. In the FPGA, the digitized gamma ray pulses and digital addresses were processed to generate data packages containing pulse arrival time, baseline value, energy value and GAPD channel ID. Finally, these data packages were saved to a 128 Mbyte on-board synchronous dynamic random access memory (SDRAM) and then transferred to a host computer for coincidence sorting and image reconstruction. In order to evaluate the functionality of the developed signal processing method, energy and timing resolutions for brain PET were measured via the placement of a 6 μCi 22Na point source at the center of the PET scanner. Furthermore the PET image of the hot rod phantom (rod diameter: from 2.5 mm to 6.5 mm) with activity of 1 mCi was simulated, and then image acquisition experiment was performed using the brain PET. Measured average energy resolution for 1152 GAPD channels and system timing resolution were 19.5% (FWHM%) and 2.7 ns (FWHM), respectively. With regard to the acquisition of the hot rod phantom image, rods could be resolved down to a diameter of 2.5 mm, which was similar to simulated results. The experimental results demonstrated that the signal processing method developed herein was successfully implemented for brain PET. This reduced the complexity, cost and developing duration for PET system relative to normal PET electronics, and it will obviously be useful for the development of high-performance investigational PET systems.

Constant Coefficient Multiplication Using Look-Up Tables

Multiplication is an important but expensive operation in most FPGA-based signal processing systems. Many techniques have been introduced for reducing the size and improving the speed of FPGA-based multipliers. Constant-coefficient multipliers are an important class of such multipliers that reduce FPGA resource requirements by exploiting constant-specific optimizations. This paper reviews and analyzes a constant coefficient multiplier that exploits the fine-grain memory resources of FPGAs by performing table look-up. Several optimizations to this multiplier are introduced and analyzed. This paper will also introduce several techniques for reducing the resources of this multiplier by exploiting modern FPGA architectural enhancements.