FPGA-based Data Acquisition Research Articles

Design of FPGA-Based Data Acquisition System for the Interferometer

In compliance with the characteristics of the reference interference system in the Fourier transform infrared spectrometer, the paper puts forward a FPGA-based data acquisition system for the signal sampling of laser interference. This system adopts SRAM as the memory and the serial port transmission technology. Under control of FPGA, data of the interference signal are successfully acquired, stored and transmitted with finite state machine as the timing control mode. The acquired interference signal of laser shows that the data acquisition system is effective.

3D virtual world remote laboratory to assist in designing advanced user defined DAQ systems based on FlexRIO and EPICS

iRIO-3DLab is a platform devised to assist developers in the design and implementation of intelligent and reconfigurable FPGA-based data acquisition systems using EPICS and FlexRIO technologies. Although these architectures are very powerful in defining the behavior of DAQ systems, this advantage comes at the price of greater difficulty in understanding how the system works, and how it should be configured and built according to the hardware available and the processing demanded by the requirements of the diagnostics. In this regard, Virtual Reality technologies are highly effective at creating rich training scenarios due to their ability to provide immersive training experiences and collaborative environments. The designed remote laboratory is based on a 3D virtual world developed in Opensim, which is accessible through a standard free 3D viewer. Using a client-server architecture, the virtual world connects with a service running in a Linux-based computer executing EPICS. Through their avatars, users interact with virtual replicas of this equipment as they would in real-life situations. Some actions can be used to simulate the behavior of a real system to enhance the training process, while others can be used to make real changes remotely in the physical system.

High-Speed Medical Imaging in 3D Ultrasound Computer Tomography

A promising candidate for sensitive imaging of breast cancer is 3D Ultrasound Computer Tomography (3D USCT). So far its clinical applicability for diagnosis has been limited by the duration of the demanding image reconstruction. In this paper we investigate how signal processing and image reconstruction can be accelerated for diagnosis by using heterogeneous hardware. Additionally, the time and costs for real-time system for a future diagnosis and therapy device is estimated. Reusing the device's built-in FPGA-based data acquisition system (DAQ) through reconfiguration results in a speed-up by a factor of 7 for signal processing and by a factor of 2 for image reconstruction. Applying cutting-edge single FPGAs and GPUs, speed-ups by a factor of 10 (FPGA) and 6 (GPU) for signal processing and 15 (FPGA) and 37 (GPU) for image reconstruction were achieved compared to a recent quad-core Intel Core-i7 CPU. Using quad-core CPUs and a cluster of eight GPUs allowed us for the first time to calculate volumes in less than 30 min with an overall speed-up by a factor of 47, enabling a first clinical study. Based on these results we extrapolated that real-time reconstruction for a therapeutic 3D USCT will be possible in the year 2020 if the trend in density follows the ITRS roadmap.

Investigation of High-Level Synthesis tools’ applicability to data acquisition systems design based on the CMS ECAL Data Concentrator Card example

High-Level Synthesis (HLS) for Field-Programmable Logic Array (FPGA) programming is becoming a practical alternative to well-established VHDL and Verilog languages. This paper describes a case study in the use of HLS tools to design FPGA-based data acquisition systems (DAQ). We will present the implementation of the CERN CMS detector ECAL Data Concentrator Card (DCC) functionality in HLS and lessons learned from using HLS design flow.The DCC functionality and a definition of the initial system-level performance requirements (latency, bandwidth, and throughput) will be presented. We will describe how its packet processing control centric algorithm was implemented with VHDL and Verilog languages. We will then show how the HLS flow could speed up design-space exploration by providing loose coupling between functions interface design and functions algorithm implementation.We conclude with results of real-life hardware tests performed with the HLS flow-generated design with a DCC Tester system.

In-treatment tests for the monitoring of proton and carbon-ion therapy with a large area PET system at CNAO

One of the most promising new radiotherapy techniques makes use of charged particles like protons and carbon ions, rather than photons. At present, there are more than 50 particle therapy centers operating worldwide, and many new centers are being constructed. Positron Emission Tomography (PET) is considered a well-established non-invasive technique to monitor range and delivered dose in patients treated with particle therapy. Nuclear interactions of the charged hadrons with the patient tissue lead to the production of β+ emitting isotopes (mainly 15O and 11C), that decay with a short lifetime producing a positron. The two 511keV annihilation photons can be detected with a PET detector. In-beam PET is particularly interesting because it could allow monitoring the ions range also during dose delivery.A large area dual head PET prototype was built and tested. The system is based on an upgraded version of the previously developed DoPET prototype. Each head covers now 15×15cm2 and is composed by 9 (3×3) independent modules. Each module consists of a 23×23 LYSO crystal matrix (2mm pitch) coupled to H8500 PMT and is readout by custom front-end and a FPGA based data acquisition electronics.Data taken at the CNAO treatment facility in Pavia with proton and carbon beams impinging on heterogeneous phantoms demonstrate the DoPET capability to detect the presence of a small air cavity in the phantom.

Development of compact DOI-measurable PET detectors for simultaneous PET/MR Imaging

It is critically needed yet challenging to develop compact PET detectors with high sensitivity and uniform, high imaging resolution for improving the performance of simultaneous PET/MR imaging, particularly for an integrated/inserted small-bore system. Using the latest “edge-less” SiPM arrays for DOI measurement using the design of dual-ended-scintillator readout, we developed several compact PET detectors suited for PET/MR imaging. Each detector consists of one LYSO array with each end coupled to a SiPM array. Multiple detectors can be seamlessly tiled together along all sides to form a large detector panel. Detectors with 1.5x1.5 and 2.0x2.0 mm crystals at 20 or 30 mm lengths were studied. Readout of individual SiPM or capacitor-based signal multiplexing was used to transfer 3D interaction position-coded analog signals through flexible-print-circuit cables to dedicated ASIC frontend electronics to output digital timing pulses that encode interaction information. These digital pulses can be transferred to, through standard LVDS cables, and decoded by a FPGA-based data acquisition positioned outside the MRI scanner for coincidence event selection. Initial detector performance measurement shows excellent crystal identification even with 30 mm long crystals, ~18% and 2.8 ns energy and timing resolutions, and around 2-3 mm DOI resolution. A large size detector panel can be scaled up with these modular detectors and different PET systems can be flexibly configured with the scalable readout electronics and data acquisition, providing an important design advantage for different system and application requirements. It is expected that standard shielding of detectors, electronics and signal transfer lines can be applied for simultaneous PET/MR imaging applications, with desired DOI measurement capability to enhance the PET performance and image quality.

Flexible DAQ card for detector systems utilizing the CoaXPress communication standard

This work concerns the design and construction of a flexible FPGA based data acquisition system aimed for particle detectors. The interface card as presented was designed for large area detectors with millions of individual readout channels. Flexibility was achieved by partitioning the design into multiple PCBs, creating a set of modular blocks, allowing the creation of a wide variety of configurations by simply stacking functional PCBs together. This way the user can easily toggle the polarity of the high voltage bias supply or switch the downstream interface from CoaXPress to PCIe or stream directly HDMI. We addressed the issues of data throughput, data buffering, bias voltage generation, trigger timing and fine tuning of the whole readout chain enabling a smooth data transmission. On the current prototype, we have wire-bonded a MediPix2 MXR quad and connected it to a XILINX FPGA. For the downstream interface, we implemented the CoaXPress communication protocol, which enables us to stream data at 3.125 Gbps to a standard PC.

Supervisory Control and FPGA Based DAQ Card

The purpose of this paper was to design the efficient, cost-effective and reliable FPGA based Data acquisition card with the smart features. Features like Web monitoring and SMS monitoring makes it better supervisory control. The Graphical User Interface (GUI) is made on the LabVIEW, which provides the very easy user interface. It cannot solely be applied in the industry, but also for the academic purpose.

Fully Digital FPGA-Based Data Acquisition System for Dual Head PET Detectors

We present the development of a new fully digital, flexible, cost-efficient data acquisition system (DAQ) suitable for dual head Positron Emission Tomography (PET) scanners for small animal imaging applications. A free-running 12 bit octal channel Analog to Digital Converter (ADC), with 65 MHz sampling rate, was used for the digitization of the detector signals. The digitized data were fed into a Spartan 6 Field Programmable Gate Array (FPGA) for event processing. An embedded system was developed for the acquisition, using Xilinx’s Embedded Development Kit (EDK) and Microblaze processor. A digital version of the Constant Fraction Discriminator (CFD) method was implemented in the FPGA, in order to achieve higher time resolution than the ADC sampling period, eliminating the need of an external mixed-signal device. The obtained information using FPGA includes: event timing, energy determination-discrimination, position determination and coincidence processing. The online processing of potential coincident events, significantly reduces the amount of data that will be transmitted to the computer. Coincident events are written temporarily to an external memory provided on a development board and are transferred to a Personal Computer (PC), via Ethernet link, for image reconstruction. Minimal post processing of the data is required prior to reconstruction. A small detector pair consisting of a BGO array coupled to a Position Sensitive Photomultiplier Tube (PSPMT) was used for the evaluation of the readout system. Obtained results prove that the proposed architecture can be used for the readout of dual head PET detectors for small animal imaging applications.

Development of An Embedded FPGA-Based Data Acquisition System Dedicated to Zero Power Reactor Noise Experiments

Abstract An embedded time interval data acquisition system (DAS) is developed for zero power reactor (ZPR) noise experiments. The system is capable of measuring the correlation or probability distribution of a random process. The design is totally implemented on a single Field Programmable Gate Array (FPGA). The architecture is tested on different FPGA platforms with different speed grades and hardware resources. Generic experimental values for time resolution and inter-event dead time of the system are 2.22 ns and 6.67 ns respectively. The DAS can record around 48-bit x 790 kS/s utilizing its built-in fast memory. The system can measure very long time intervals due to its 48-bit timing structure design. As the architecture can work on a typical FPGA, this is a low cost experimental tool and needs little time to be established. In addition, revisions are easily possible through its reprogramming capability. The performance of the system is checked and verified experimentally.

FPGA-based 10-Gbit Ethernet Data Acquisition Interface for the Upgraded Electronics of the ATLAS Liquid Argon Calorimeters

A stepwise upgrade of the LHC is foreseen starting now until the year 2023 to increase the instantaneous luminosity up to five times of its design value. It implies a challenge for the ATLAS experiment coping with the expected event pile-up, especially for the Level-1 calorimeter trigger system. In order to keep the trigger rates within the limited bandwidth new algorithms have to be applied which in turn requires an upgrade of the ATLAS Liquid Argon calorimeter trigger readout electronics. Towards this upgrade, the ATLAS Liquid Argon calorimeter group develops a high-speed data acquisition interface in ATCA standard using commercial hardware instead of complex and expensive in-house developments where possible. This paper gives an overview of the general concepts of the DAQ interface, the engaged technologies and the current status of the development efforts for an FPGA based fast data link with a standard 10 Gbps Ethernet protocol which may also be useful for DAQ systems of other high energy physics experiments.

FPGA based data acquisition system for COMPASS experiment

This paper presents the current data acquisition system (DAQ) of the COMPASS experiment at CERN and discusses development of a new DAQ. The aim of the new DAQ is to substitute software event building by structure composed of special FPGA cards that will do the event building. The software part of the new DAQ is robust multinode system with high emphasis on reliability. It is based on state machines and implemented in C++ with usage of the QT framework, the DIM library, and the IPBus technology. A prototype of the system has been developed and tested. The new DAQ software fulfills given requirements.

MO‐G‐17A‐01: Innovative High‐Performance PET Imaging System for Preclinical Imaging and Translational Researches

Purpose:To develop a practical and compact preclinical PET with innovative technologies for substantially improved imaging performance required for the advanced imaging applications.Methods:Several key components of detector, readout electronics and data acquisition have been developed and evaluated for achieving leapfrogged imaging performance over a prototype animal PET we had developed. The new detector module consists of an 8×8 array of 1.5×1.5×30 mm3 LYSO scintillators with each end coupled to a latest 4×4 array of 3×3 mm2 Silicon Photomultipliers (with ∼0.2 mm insensitive gap between pixels) through a 2.0 mm thick transparent light spreader. Scintillator surface and reflector/coupling were designed and fabricated to reserve air‐gap to achieve higher depth‐of‐interaction (DOI) resolution and other detector performance. Front‐end readout electronics with upgraded 16‐ch ASIC was newly developed and tested, so as the compact and high density FPGA based data acquisition and transfer system targeting 10M/s coincidence counting rate with low power consumption. The new detector module performance of energy, timing and DOI resolutions with the data acquisition system were evaluated. Initial Na‐22 point source image was acquired with 2 rotating detectors to assess the system imaging capability.Results:No insensitive gaps at the detector edge and thus it is capable for tiling to a large‐scale detector panel. All 64 crystals inside the detector were clearly separated from a flood‐source image. Measured energy, timing, and DOI resolutions are around 17%, 2.7 ns and 1.96 mm (mean value). Point source image is acquired successfully without detector/electronics calibration and data correction.Conclusion:Newly developed advanced detector and readout electronics will be enable achieving targeted scalable and compact PET system in stationary configuration with >15% sensitivity, ∼1.3 mm uniform imaging resolution, and fast acquisition counting rate capability for substantially improved imaging and quantification performance for small animal imaging and image‐guided radiotherapy applications.This work was supported by a research award RP120326 from Cancer Prevention and Research Institute of Texas.

Graphical Hardware Description as a High-Level Design Entry Method for FPGA-Based Data Acquisition Systems

Probably one of the most significant developments in the field of software-defined multifunction data acquisition systems and devices is the employment of FPGA (Field-Programmable GateArray) technology, resulting in a tremendous digital processing potential close to the I/O pin. FPGA technology is based on reconfigurable semiconductor devices which can be employed as processing targets in heterogeneous computing architectures for a variety of data acquisition applications. They can primarily be characterized by generic properties, such as deterministic execution, inherent parallelism, fast processing speed and high availability, stability and reliability. Therefore FPGAs areparticularly suitable for use in “intelligent” data acquisition applications that require either in-line digital signal co-processing or real-time system emulation in the field of advanced control, protocol aware communication, hardware-in-the-loop (HIL) as well as RF and wireless test. From the perspective of a domain expert however, primarily being focused on developing applications and algorithms, simple and intuitive design entry methods and tools are required that facilitate the FPGA configuration and design entry process. Traditional FPGA design entry methods and commercially available tools assume a comprehensive knowledge of hardware description languages (HDL),such as VHDL or Verilog®, and implement a process or function at register-level. In contrast, graphical hardware description languages for FPGAs, such as the integrated development environment NI LabVIEW® with FPGA module extension, abstract the design process by means of graphical objects, I/O nodes and interconnecting wires that represent the FPGA’s IP and implement processes, timing, I/O integration and data flow. This paper discusses the advantages of graphical system design for FPGAs over text-based alternatives, introduces interfaces for the integration of 3rd party IP, all backed up by a detailed illustration of a COTS FPGA-based multifunction DAQ target compared to a traditional DAQ architecture.

A new FPGA-based trigger/DAQ system for the MTV experiment at TRIUMF

A new FPGA based data acquisition (DAQ) and trigger combined system is developed for the MTV experiment (Mott Polarimetry for T-Violation Experiment). The MTV experiment measures backward Mott scattering events by detecting the incident and scattered tracks using a drift chamber. For the backward scattering probability is as small as less than 0.1%, efficient triggering system is required to select the desired events. An intelligent Level-2 trigger system reading hitting pattern together with its digital readout system are built in a custom FPGA system. In this paper, design overview and results from performance tests are described.

Design of a Real-Time FPGA-Based Data Acquisition Architecture for the LabPET II: An APD-Based Scanner Dedicated to Small Animal PET Imaging

To achieve submillimetric spatial resolution, a new detection block has been designed for the LabPET II, a small animal PET scanner being developed at Universite de Sherbrooke. Each detection block consists of 2 arrays of 4×8 avalanche photodiodes (APD) individually coupled to an 8×8 scintillator array, to form 64 independent and parallel DAQ channels. This new detection block entails an 8-fold increase in pixel density compared to the LabPET™ I. A 64-channel mixed-signal Application Specified Integrated Circuit (ASIC) was designed to extract relevant PET data in real time from the LabPET II detection blocks. The ASIC is expected to support up to 3000 PET events/sec per channel. In order to interface the ASICs forming the PET camera with the storage units, a real-time FPGA-based digital DAQ system was designed. The DAQ system allows event harvesting, processing and transmission to a distant computer for image reconstruction as well as system programming and calibration. Real-time event processing embedded in the DAQ includes energy computation using a time-over-threshold (TOT) conversion scheme, timing corrections and event sorting trees. A real-time coincidence engine analyzes events and only keeps relevant information to minimize data throughput and post-acquisition data processing. The architecture consists of 3 layers of FPGA-based electronics wired through gigabit links: a Front-End board extracts timing and energy along with a pixel address, a Hub board sorts incoming events chronologically and a Coincidence board matches coincident events and copes with randoms estimation. Every FPGA in the different layers is accessible through an Ethernet link. The real-time digital architecture sustains the required throughput of ~111 Mevents/s for a ∼37000 channels scanner configuration.

A Labview based FPGA data acquisition with integrated stage and beam transport control

We report on a new FPGA based data acquisition system developed for the CSIRO Nuclear Microprobe (NMP) which is tightly integrated with both target positioning and beam transport. The data acquisition system called MicrodaQ is based on National Instruments Labview FPGA and numerous instrumentation modules spread over several PC’s. Beam transport uses a feedback control loop to optimise current on target for long unmanned experiments. These upgrades are discussed in detail and an example of the systems use for μ-Particle Induced X-ray Emission (PIXE) analysis on a Doriri apatite is briefly described.

Design of Data Acquisition and Storage System for Digital and Analog Signal Based on FPGA

This paper mainly introduces a FPGA-based data acquisition system which is designed to acquire multi-channel analog signal and one channel digital signal. Analog data and digital data are stored into a FLASH memory in a mixed frame format. When the acquisition finished, the data in the FLASH was read out via the LVDS communication interface to a data-read device, and the host computer receives the data through the USB bus, so the subsequent data processing and analysis can be accomplished and the information we needed can be got. The design is applied successfully to a remote measurement system, and the data acquired is reliable and precise.

A Spartan 6 FPGA-based data acquisition system for dedicated imagers in nuclear medicine**This paper was originally submitted for inclusion in the special feature on Imaging Systems and Techniques 2011.

We present the development of a four-channel low-cost hardware system for data acquisition, with application in dedicated nuclear medicine imagers. A 12 bit octal channel high-speed analogue to digital converter, with up to 65 Msps sampling rate, was used for the digitization of analogue signals. The digitized data are fed into a field programmable gate array (FPGA), which contains an interface to a bank of double data rate 2 (DDR2)-type memory. The FPGA processes the digitized data and stores the results into the DDR2. An ethernet link was used for data transmission to a personal computer. The embedded system was designed using Xilinx's embedded development kit (EDK) and was based on Xilinx's Microblaze soft-core processor. The system has been evaluated using two different discrete optical detector arrays (a position-sensitive photomultiplier tube and a silicon photomultiplier) with two different pixelated scintillator arrays (BGO, LSO:Ce). The energy resolution for both detectors was approximately 25%. A clear identification of all crystal elements was achieved in all cases. The data rate of the system with this implementation can reach 60 Mbits s−1. The results have shown that this FPGA data acquisition system is a compact and flexible solution for single-photon-detection applications.

Power law temporal dependence of InGaAs/InP SPAD afterpulsing

The characterization and analysis of afterpulsing behavior in InGaAs/InP single photon avalanche diodes (SPADs) is reported for gating frequencies between 10 and 50 MHz. Gating in this frequency range was accomplished using a matched delay line technique to achieve parasitic transient cancellation, and FPGA-based data acquisition firmware was implemented to provide an efficient, flexible multiple-gate sequencing methodology for obtaining the dependence of afterpulse probability P ap on hold-off time T ho. We show that the detrapping times extracted from the canonical exponential fitting of P ap(T ho) have no physical significance, and we propose an alternative description of the measured data, which is accurately fit with the simple power law behavior P ap ∝ with α ∼ 1.2 ± 0.2. We discuss the physical implications of this functional form, including what it may indicate about trap defect distributions and other possible origins of this power law behavior.