Four-stage Low Noise Amplifier Research Articles

140 GHz 40 nm CMOS 저잡음 증폭기

This paper presents a 140 GHz four-stage low-noise amplifier in a 40 nm CMOS process. The input, output, and interstage of the amplifier were matched using a microstrip line (composed of lowest two metal layers and a top metal layer). An AC ground using bypass capacitors was formed to minimize the effect of the internal inductance of the external power supply. The number of capacitors was chosen considering an ideal AC ground case for the ground and noise figures. D-band on-wafer measurements indicated a gain of 15.6 dB, noise figure of 8.8 dB, and power consumption of 18 mW. The circuit area, including the pads, was 490 μm×430 μm.

A Low Switching-Loss W-Band Radiometer Utilizing a Single-Pole-Double-Throw Distributed Amplifier in 0.13-<formula formulatype="inline"> <tex Notation="TeX">$\mu{\hbox {m}}$</tex> </formula> SiGe BiCMOS

This paper presents a low switching-loss Dicke radiometer for W-band passive imaging systems. The equivalent switching loss introduced by the passive single-pole-double-throw (SPDT) switch in the conventional radiometer is significantly reduced by the proposed single-pole-double-throw distributed amplifier (SPDT-DA), which leads to radical improvement on the receiver’s noise performance. The Dicke radiometer consisting of a SPDT-DA, a four-stage low noise amplifier (LNA) and a power detector is fully integrated in a 0.13- $\mu{\hbox {m}}$ SiGe BiCMOS chip. With the 0.93-dB equivalent switching loss at 91 GHz of the SPDT-DA, the total noise figure (NF) of 8.4 dB at 91 GHz is achieved by the SPDT-DA followed by the LNA. With a power consumption of 28.5 mW, the radiometer obtains an overall RF gain of 42 dB and a noise equivalent temperature difference (NETD) of 0.21 K with 30-ms integration time. The two-dimensional imaging experiment with object distance of 0.7 m is successfully carried out with the radiometer chip.

Stabilization of millimeter‐wave multistage amplifier using amplitude‐and‐phase setting circuits

AbstractThis paper derives the conditions to be satisfied by the amplifier in each stage of a multistage amplifier in order for it to be absolutely stable. It is shown that the stability factor K of each stage need not be larger than unity except for the initial and last stages. By means of this condition, it is possible to improve the gain in comparison to the conventional method in which the amplifiers in all stages are made K > 1 and then are cascaded. In the millimeter wave range, where device performance deteriorates, the gain reduction due to stable design is significant. Therefore, the present conclusion is extremely effective for the design of multistage amplifiers in the millimeter wave range. Further, in this paper, a new design method is presented that assures absolute stability of a multistage amplifier that consists of unit amplifiers, each of which has a stability factor K of less than 1. In this method, an amplitude‐and‐phase setting circuit consisting of transmission lines and resistors is connected at the output of each stage and the transmission amplitude and phase are adjusted in such a way that the stability condition derived in this paper is satisfied. It is shown that there exists an optimum transmission phase maximizing the gain of the multistage amplifier. Finally, the proposed method is applied to the design of a U‐band four‐stage low‐noise amplifier. © 2001 Scripta Technica, Electron Comm Jpn Pt 2, 84(12): 26–36, 2001

X-band MMIC amplifier with pulse-doped GaAs MESFET's

The design and test of an X-band monolithic four-stage low-noise amplifier (LNA) with 0.5 mu m-gate pulse-doped GaAs MESFETs for application in a direct broadcast satellite (DBS) converter is presented. The key feature of the research is a detailed demonstration of the advantages of using series feedback with experiments and simulations. This LNA shows an excellent input VSWR match under 1.4 as well as a noise figure of 1.67 dB and a gain of 24 dB at 12 GHz. The noise figure, the gain and VSWRs exhibit very little bias current dependence due to the exceptional features of the pulse-doped structure FETs and the optimized circuit design. Insensitivity to bias current implies performance stability in the face of process fluctuations. Thus, the yield of chips with noise figures of less than 2.0 dB is as high as 62.5%, and the variations of gain and VSWR are highly uniform as well. >