140 GHz 40 nm CMOS 저잡음 증폭기

Abstract

This paper presents a 140 GHz four-stage low-noise amplifier in a 40 nm CMOS process. The input, output, and interstage of the amplifier were matched using a microstrip line (composed of lowest two metal layers and a top metal layer). An AC ground using bypass capacitors was formed to minimize the effect of the internal inductance of the external power supply. The number of capacitors was chosen considering an ideal AC ground case for the ground and noise figures. D-band on-wafer measurements indicated a gain of 15.6 dB, noise figure of 8.8 dB, and power consumption of 18 mW. The circuit area, including the pads, was 490 μm×430 μm.