Four-quadrant Analog Multiplier Research Articles

New Electronically Tunable Four-Quadrant Analog Multiplier Employing Single EXCCCII and Its Applications

New Electronically Tunable Four-Quadrant Analog Multiplier Employing Single EXCCCII and Its Applications

Hybrid Analog Computer for Modeling Nonlinear Dynamical Systems: The Complete Cookbook

This paper describes a design process for a universal development kit based on an analog computer concept that can model the dynamics of an arbitrarily complex dynamical system up to the fourth order. The constructed development kit contains digital blocks and associated analog-to-digital and digital-to-analog converters (ADCs and DAC), such that multiple-segmented piecewise-linear input-output characteristics can be used for the synthesis of the prescribed mathematical model. Polynomial input-output curves can be implemented easily by four-quadrant analog multipliers. The proposed kit was verified through several experimental scenarios, starting with simple sinusoidal oscillators and ending with generators of continuous-time robust chaotic attractors. The description of each individual part of the development kit is accompanied by links to technical documentation, allowing skilled readers in the construction of electronic systems to replicate the proposed functional example. For this purpose, the electrical scheme of the hybrid analog computer and all important source codes are available online.

Current-controlled grounded memristor emulator circuit based on analog multiplier

This paper proposes a current-controlled grounded memristor emulator circuit based on single four-quadrant analog multiplier, a resistor and a capacitor. The behavioral model of the proposed emulator circuit is analyzed, highlighting its characteristics. Experimental results are given to investigate its ability for different operating frequencies and they are in accordance with theoretical analysis and simulation results. By using a divider circuit, the memristance variation in the time domain is obtained. It is observed that the pinched hysteresis loop at high frequency loses symmetry due in part to the shift that introduces a multiplication of sinusoidal signals.

A four-quadrant analog multiplier using DTMOS for low power applications

ABSTRACT The four-quadrant analog multipliers (FQAM) are widely used in signal processing applications such as amplitude modulation, frequency doubling, and adaptive filters. In this paper, a FQAM has been realised in dynamic threshold voltage MOSFET (DTMOS) technology. It relies on the square-law characteristics of the MOS transistor. Several simulations have been carried out to assess the operation of the proposed FQAM. The supply voltage is set to ±0.2 V, and 68 µW power consumption is determined. The input signal can be applied to the full scale of the supply voltage. The bandwidth is 22.86 MHz, and the output signal’s total harmonic distortion (THD) is less than 2%. Intermodulation products of the output signal have been calculated. Monte Carlo and temperature simulations have been performed in a way that confirms the robustness of the circuit against the technological spread. In summary, low power consumption, wide bandwidth, and linearity are the advantages of the proposed circuit.

Four quadrant analog multiplier based memristor emulator using single active element

This paper presents a novel Four Quadrant Analog Multiplier (FQAM) circuit and its applications using a single active element Current Differencing Transconductance Amplifier (CDTA) and two NMOS. This circuit has a cascadability feature as it produces current and voltage outputs at high and low impedance ports, respectively. It offers additional features such as resistor-less realization, operability in voltage and trans-conductance mode, and configurable structure. Further, the FQAM circuit is configured to develop a memristor emulator based on the proposed mathematical analogy. The proposed memristor circuit contains active elements (one CDTA, two NMOS, and one Inverting Voltage buffer) and only one grounded capacitor. It offers tunability using the transconductance gain of the CDTA block. Also, the proposed memristor emulator circuit doesn’t contain any additional multiplier block. The emulator circuit can be operated in both the Incremental and the Decremental mode of memristance variation. The results demonstrate the non-volatile property as well as hysteresis behavior for the wide frequency range. The effects of statistical variation in passive component, threshold voltage, and aspect ratios on the proposed circuits using Monte-Carlo simulation have been estimated. Also, the impact of non-idealities and the parasitic effects of the CDTA on the proposed circuits are investigated. In last, the capacitor-less version of the memristor emulator and its hysteresis characteristics have been demonstrated. The simulation results obtained using HSPICE, are agreed well with the theoretical analysis.

A DTMOS based Four-Quadrant Analog Multiplier

A DTMOS based Four-Quadrant Analog Multiplier

An Analogue Multiplier using CNTFET Technology

The endeavor to overcome problems of complementary metal oxide semiconductor technology makes the advent of Carbon nanotube field effect transistor (CNTFET). Improvement of structure transistor CNTFET makes higher mobility and electrostatics of gate electrons. Therefore, many analog circuits are now designed based on CNTFET technology. This paper presents a low power current mode four-quadrant analog multiplier based on CNTFET and CMOS technologies. All simulations were done with the synopsys Hspice simulator using 32nm CNTFET model from Stanford University and 32nm CMOS from PTM library at a supply voltage of 3.3 v. It was shown that the simulation of a multiplier based on CNTFET technology performs better than a multiplier based on CMOS technology.

A VDTA-based robust electronically tunable memristor emulator circuit

In this paper, a fully-integrated tunable grounded memristor emulator circuit based on voltage differencing transconductance amplifier (VDTA) has been proposed. The proposed memristor emulator circuit utilizes two VDTA active building blocks, two grounded resistors, a grounded capacitor and a four-quadrant analog multiplier. The working concept along with the detailed derivation of the mathematical model of the circuit has been discussed numerically and analytically to validate the operation of the proposed emulator. The operations of the proposed emulator circuit, as governed by the established model, have been verified by performing simulations in Cadence Virtuoso at 45 nm technology node. Robustness analyses performed, reveal significant process-variation tolerance at deep sub-micron technology node.

High Performance Four-Quadrant Analog Multiplier Using DXCCII

This paper presents a four-quadrant analog multiplier using a single dual-X second-generation current conveyor (DXCCII). The proposed analog multiplier employs two NMOS transistors operating in triode region, besides a single DXCCII. The performances of the proposed analog multiplier are verified through PSPICE simulation using 0.18 μm TSMC CMOS process parameters. Simulation results reveal that the circuit has a − 3 dB bandwidth of 19.30 GHz and 0.79% total harmonic distortion for the input voltage of 250 mV. The application of proposed analog multiplier as a squarer, for amplitude modulation and as frequency doubler are also included. The detailed comparisons with existing literature justify the novelty of the proposed circuit.

A novel CNFET based tunable memristor emulator

This paper presents a novel carbon nanotube field effect transistor (CNFET) based memristor emulator circuit. The proposed memristor emulator circuit utilizes voltage differencing transconductance amplifier (VDTA) as an active building block. The emulator circuit employs two VDTAs, two grounded resistors, one grounded capacitor and one four-quadrant analog multiplier. The working concept along with the detailed derivation of the mathematical model of the circuit has been discussed analytically and numerically to confirm the operation of the circuit. The operation of the proposed emulator circuit, as governed by the established equations, has been verified by performing simulations using 32-nm Stanford CNFET model. Further, the robustness of the emulator circuit has been investigated by subjecting it to process and temperature variations. Variability analyses reveals significant tolerance towards aforementioned fluctuations in parameters.

Compact Design of High-Speed Low-Error Four-Quadrant Current Multiplier with Reduced Power Dissipation

In this paper, a compact low-power, high-speed, low-error four-quadrant analog multiplier is proposed using a new simple current squarer circuit. The new squarer circuit consists of an NMOS transistor, which operates in saturation region, plus a resistor. The proposed multiplier has a balanced structure composed of four squarer cells and a simple current mirror. This multiplier also has the important property of not using bias currents which results in greatly reduced power. The performance of the proposed design (for passive and active realization of the resistors) has been simulated using HSPICE software in 0.18[Formula: see text][Formula: see text]m TSMC (level-49) CMOS technology. Simulation results with [Formula: see text]-V DC supply voltages show (for passive realization) that the maximum linearity error is 0.35%, the [Formula: see text][Formula: see text]dB bandwidth (BW) is 903[Formula: see text]MHz, the total harmonic distortion (THD) is 0.3% (at 1[Formula: see text]MHz), and the maximum and static power consumption are [Formula: see text]W and [Formula: see text]W, respectively. Also, post-layout simulation results are extracted, which give the maximum linearity error as 0.4%, the [Formula: see text][Formula: see text]dB BW as 657[Formula: see text]MHz and the THD as 0.35%, as well. Moreover, Monte Carlo analysis are performed to verify the satisfactory robustness and reliability of the proposed work’s performance.

Voltage Differencing Buffered Amplifier based Voltage Mode Four Quadrant Analog Multiplier and its Applications

In this paper a voltage mode four quadrant analog multiplier (FQAM) using voltage differencing buffered amplifier (VDBA) based on quarter square algebraic identity is presented. In the proposed FQAM the passive resistor can be implemented using MOSFETs operating in saturationregion thereby making it suitable for integration. The effect of non idealities of VDBA has also been analyzed in this paper. Theoretical propositions are verified through SPICE simulations at 0.18μm CMOS technology node and the simulation results are found in close agreement with theoretical values. The supply voltage is taken as ± 1V and the value of the bias current is set to 40µA.The simulated total harmonic distortion (THD) is observed to be under 3% and the total power dissipation is found as 627µW. The workability of the proposed FQAM is also tested through two applications, namely, an amplitude modulator and a rectifier. The simulated results corroborate the theoretical propositions.

Gate and Bulk-Driven Four-Quadrant CMOS Analog Multiplier

This work presents and validates the design of a four-quadrant analog multiplier based on the bulk-driven technique. Using the source–gate as well as the bulk–source voltages of a PMOS transistor as input ports, the multiplication task can be achieved. The AC signals are injected into the bulk terminals by means of a very-low-frequency programmable high-pass RC network which also serves to set its proper DC operation point. Although two RC networks are required, this multiplication cell is composed of only seven PMOS transistors and two coupling capacitors which makes it a very compact circuit. Furthermore, no preprocessed signals like the sum of $$\pm \,v_x \pm \,v_y$$ are required at the input ports. The implemented circuit shows a bandwidth of 50 MHz for an output capacitance of 40 pF and a THD lower than 1 $$\%$$ for gate/bulk input amplitudes below 0.2 Vp. The power consumption of the multiplication core is 660 $$\upmu $$ W and 2.6 mW including output buffers. In order to simulate and fabricate this circuit, an ON Semi 0.50 $$\upmu $$ m CMOS standard technology is used, showing a silicon area consumption of $$280\,\upmu \hbox {m} \times 400\,\upmu $$ m including output buffers. The proposed multiplier is suitable for biomedical, AM modulation, base-band modulation and analog computation.

Ultra-low voltage and low-power voltage-mode DTMOS-based four-quadrant analog multiplier

This paper presents a new four-quadrant analog multiplier based on a dynamic threshold MOS (DTMOS). The attractive features of this DTMOS transistor-based multiplier are its supply voltages and total power consumption, which were determined as ± 0.2 V and 18.4 nW, respectively. In addition, the study found no influences of the bulk effect of the transistors used in the proposed multiplier circuit. The layout of the four-quadrant analog multiplier occupied an active area of 44.6 µm × 21.93 µm and was drawn using Cadence Environment software, while the post-layout simulation results were performed using Cadence Environment with 0.18 µm TSMC CMOS technology parameters. All theoretical results and post-layout simulations confirmed the performance of the proposed circuit.

A novel current-mode low-power adjustable wide input range four-quadrant analog multiplier

In this paper, a novel current mode enhanced input range four-quadrant analog multiplier is presented. The proposed class AB based translinear current squarer allows the designer to control the input range via a digital code. Moreover, the proposed scheme improves the linearity of the circuit and has a high robustness against process variations. The Post-layout and Monte Carlo simulations of the multiplier in a 0.18 μm standard CMOS technology show an input range of (1+m) × 10 μA (where ‘m’ is an adjustable parameter), a THD of 1% (@1 MHz), a −3 dB bandwidth of 332.3 MHz (for m = 3) and a power consumption of 186 μW.

Wide bandwidth CMOS four-quadrant mixed mode analogue multiplier using a second generation current conveyor circuit

This paper presents a new realization for a CMOS four-quadrant analogue multiplier. The proposed circuit is composed of three second generation current conveyor circuits (CCII), two NMOS transistors operating in the linear region, and four passive resistances. It can be operated in current mode and voltage mode without changing the circuit topology. The simulations results of the proposed mixed mode multiplier are verified by TSPICE simulator based on the BSIM3v3 transistor model for TSMC 0.18 $\mu $m CMOS process available from MOSIS at 25 $^{\circ}$C with $\pm $0.8 V supply voltage. Through the use of resistive compensation with different passive resistance values, the voltage mode responses present $\pm $0.25 V dynamic range with THD less than 0.114% and wide bandwidth extended from 3.42 GHz to 4.1 GHz. The current mode responses show $\pm $150 $\mu $A dynamic range with a maximum THD value about 0.083% and large bandwidth expanded from 2.67 GHz to 3.12 GHz.

Low power FGMOS-based four-quadrant current multiplier circuits

In this paper, low-power, high-speed four-quadrant analog multiplier circuits have been presented, based on simple current squarer circuits. The squarer circuits consist of a floating-gate MOS transistor, operating in saturation region plus a resistor. These multipliers have a unique property of greatly reduced power as they do not have any bias currents. For performance evaluation, the designs are simulated using HSPICE software in 0.18 µm (level-49 parameters) TSMC CMOS technology. Using ± 0.5 V DC supply voltages for the first design, the simulation resulted in a maximum linearity error of 0.8%, the − 3 dB bandwidth of 635 MHz, the Total Harmonic Distortion of 0.57% (at 1 MHz), and maximum and static power consumption of 40.4 and 5.75 µW, respectively. Corresponding values for the second design with 1 V DC supply voltage are 0.4%, 394.8 MHz, 0.72%, 44 and 11.4 µW, respectively. Furthermore, in order to verify the robustness and reliability of the proposed works, Monte Carlo analysis are performed. For the mentioned analysis, 5% variations in channel width and length, gate oxide thickness and threshold voltage of all transistors and resistance values are considered.

A Novel Realization of Low-Power and Low-Distortion Multiplier Circuit with Improved Dynamic Range

A novel topology of four-quadrant analog multiplier circuit is presented in this paper. The voltage mode technique is employed to design the circuit in CMOS technology. The dynamic input and output ranges of the circuit are improved owing to the fact that the circuit works in the saturation region not in weak inversion. Also the proposed multiplier is suitable for low voltage operation and its power consumption is relatively low. In order to verify the performance of the proposed circuit, performance of the circuit affected by second order effects including transistor mismatch and mobility reduction is analyzed in detail. It will be shown that any conceivable mismatch in the transistor parameters leads to second harmonic distortion. Additionally, the effect of mobility reduction in the third harmonic distortion will be computed. In order to simulate the circuit, Cadence and HSPICE software are used with TSMC level 49 (BSIM3v3) parameters for 0.18 μm CMOS technology, where under supply voltage of 1.5 V, total power consumption is 44 µW, the corresponding average nonlinearity remains as low as 1 %, and the input range of the circuit is ± 400 mV.

An Offset-free High linear Low Power High Speed Four-Quadrant MTL Multiplier

In this paper a new CMOS current-mode four-quadrant analog multiplier circuit is proposed. The major advantages of this design are high linearity, high speed and low power consumption. Removing dc offset is the most important improvement in this topology. The circuit is designed with 1.8V supply voltage and is simulated using HSPICE simulator by level 49 parameters in 0.18µm standard CMOS TSMC technology. The aspect ratios of the MOSFETs are optimized using Evolutionary algorithm by MATLAB. The simulation results of this analog multiplier demonstrate a maximum linearity error of 2.6%, a THD of 1.77%, maximum power consumption of 157 µW, -3dB bandwidth of 241MHz and almost free from dc offset.

A Novel Cubic Generator Realised by CCIII-based Four Quadrant Analog Multiplier and Divider

The objective of this paper is to present a novel cubic generator circuit using four quadrant analog multiplier and divider based on third generation current conveyor. A well-established approach has been utilized to implement the new fourquadrant analog multiplier and divider using CCIII exhibiting a larger usable bandwidth. Some additional, relevant, nonlinear applications of CCIII-based four-quadrant analog multiplier and divider have also been worked out to demonstrate its usefulness. PSPICE simulations have been carried out to validate the theoretical findings of the proposed novel cubic generator and other presented circuit configurations. Applications of the new CCIII-based multiplier and divider circuits of this paper have been shown to realize amplitude modulation, squarer and finally the novel cubic generator.Keywords: Non-Linear circuits, Analog Multiplier, Analog Divider, Third generation current conveyor, Cubic generator