Forward Equalizer Research Articles

DFE Error Propagation Mitigation using Feed Forward Equalizer and Forward Error Correction in 25Gb/s NRZ Transceiver

DFE Error Propagation Mitigation using Feed Forward Equalizer and Forward Error Correction in 25Gb/s NRZ Transceiver

Adaptive parallel decision deep neural network for high-speed equalization.

The equalization plays a pivotal role in modern high-speed optical wire-line transmission. Taking advantage of the digital signal processing architecture, the deep neural network (DNN) is introduced to realize the feedback-free signaling, which has no processing speed ceiling due to the timing constraint on the feedback path. To save the hardware resource of a DNN equalizer, a parallel decision DNN is proposed in this paper. By replacing the soft-max decision layer with hard decision layer, multi-symbol can be processed within one neural network. The neuron increment during parallelization is only linear with the layer count, rather than the neuron count in the case of duplication. The simulation results show that the optimized new architecture has competitive performance with the traditional 2-tap decision feedback equalizer architecture with 15-tap feed forward equalizer at a 28GBd, or even 56GBd, four-level pulse amplitude modulation signal with 30dB loss. And the training convergency of the proposed equalizer is much faster than its traditional counterpart. An adaptive mechanism of the network parameter based on forward error correction is also studied.

Electronic dispersion compensation and functional link neural network equalization for IM/DD links

Short-reach fiber optical links employing intensity modulation (IM) at the transmitter (Tx) and direct detection (DD) at the receiver (Rx), suffer from linear and nonlinear sources of impairments due to the interaction of chromatic dispersion (CD) with DD. In this article, joint electronic dispersion compensation (EDC) at the Tx, using two distinct Gerchberg–Saxton(GS) based approaches, and at the Rx, using a functional link neural network (FLNN) equalizer is demonstrated for IM/DD transmission. The first Tx approach utilizes the modified iterative GS algorithm, which partially mitigate linear and nonlinear sources of inter-symbol interference (ISI). The second Tx pre-EDC approach only pre-compensates for the linear power fading effect through implementing a GS based finite impulse response (FIR) filter. At the Rx, a T/2-spaced or T-spaced adaptive post-feed forward equalizer (FFE) is employed to fully compensate residual chromatic dispersion prior to attempting nonlinear equalization. Furthermore, a Volterra nonlinear equalizer (VNLE) is introduced to benchmark the performance and complexity of the FLNN, Subsequently, either a FLNN or a VNLE are utilized for nonlinear system identification and subsequent post-equalization mitigating uncompensated nonlinear sources of ISI. The FLNN nonlinear taps resulting from the functional expansion block are optimized using the recursive least square (RLS) algorithm. The Tx-FIR and Rx-FLNN enable 112 Gbit/s non-return to zero (NRZ) on–off keying (OOK) transmission over 20 km of single mode fiber (SMF) and 112 Gbit/s 4-level pulse-amplitude modulation (PAM-4) transmission over 10 km of SMF. It is shown that the use of Tx pre-EDC reduces the complexity of the required equalization at the Rx. In addition, the FLNN was found to offer a 74% reduction in computational complexity relative to the third-order VNLE.

A 100-Gb/s PAM-4 DSP in 28-nm CMOS for Serdes Receiver

This paper presents a dedicated digital signal process (DSP) for four pulse amplitude modulation (PAM4) SerDes receivers. It is targeted to implement data recovery and adaptive equalization under ultra-high-speed and large channel attenuation with a small area and high power efficiency. The DSP consists of a clock data recovery (CDR), a 16-tap feed forward equalizer (FFE), a 1-tap decision feedback equalizer (DFE), and an automatic adaptation engine. An adaptive least mean square (LMS) algorithm is utilized to make the system more intelligent in calculating tap coefficients of the FFE and DFE. To address the timing limitation associated with traditional digital DFE that cannot handle large amounts of parallel data at a high speed, speculative techniques and a customized 4-to-1 multiplexer (MUX) unit are employed to remove the summation time and reduce the selection time, respectively. A first-order sigma-delta modulator is used to replace the traditional moving average to calculate average voltages, which could prominently save the hardware resources and power consumption. Additionally, the influence of input quantization resolution on the equalization ability is analyzed. Implemented in a 28-nm CMOS, the DSP could compensate for up to 33-dB loss at 100 Gb/s with a power consumption of 7.22 pJ/bit.

200 Gbps/λ PON Downstream C-Band Direct-Detection Links with ≥29 dB Power Budget

In this paper we present the simulative analysis of a 200 Gbps per wavelength (λ) 8-level pulse amplitude modulation (PAM-8) downstream communication over up to 20 km single mode fiber (SMF) in C-band based on direct detection (DD) achieving at least a 29 dB link power budget in a PON environment. We use chromatic dispersion digital pre-compensation (CD-DPC) and a dual-arm in-phase and quadrature Mach–Zehnder modulator (IQ-MZM) at the optical line termination (OLT) side, while preserving DD in the optical network unit (ONU). Three receiver digital-signal-processing (DSP) options are analyzed and compared: square-root-like technique (SQRT) in combination with a feed forward equalizer (FFE) and a decision feedback equalizer (DFE), the Volterra nonlinear equalizer (VNLE), and the SQRT in combination with the VNLE. The SQRT can be applied in combination with the VNLE to decrease the receiver DSP complexity while maintaining the required system performance. We show that PAM-8 with CD-DPC and the SQRT in combination with the VNLE is a feasible solution for 200 Gbps per λ downstream C-band transmission for PON.

Net 220 Gbps/λ IM/DD Transmssion in O-Band and C-Band With Silicon Photonic Traveling-Wave MZM

We present the design and characterization of O-band and C-band silicon photonic (SiP) traveling wave Mach-Zehnder modulators (TW-MZM) allowing 220 Gbps/λ net rate operation. The designed modulators show over 45 GHz 3-dB E-O bandwidth with a single-segment design. In the O-band, with simple linear feed forward equalization, we transmit net 203 (200) Gbps signal over 2 km (10 km) of single-mode fiber (SMF) below the hard-decision forward error correction (HD-FEC) BER threshold of 3.8 × 10−3. With the aid of nonlinear Volterra equalizer and one 2.3Vpp driving signal, we transmit net 225 (216) Gbps PAM8 signals assuming 20% overhead soft-decision FEC with a normalized general mutual information (NGMI) threshold of 0.8798 over 2 km (10 km) of SMF. The C-band design enables net 220 Gbps in B2B and net 215 Gbps over 500 m of SMF above the specified NGMI threshold. These results are the highest reported net rate for SiP MZM in an intensity modulation direct-detection (IM/DD) system, fabricated entirely in a commercial foundry.

An Energy-Efficient 3Gb/s PAM4 Full-Duplex Transmitter With 2-Tap Feed Forward Equalizer

We present a full-duplex 3 Gb/s PAM4 voltage-mode transmitter with an embedded 2-tap feed forward equalizer. In full-duplex mode, the transmitter employs an echo canceller to cancel the locally transmitted signal and recover the signal from the far-end. The transmitter achieves energy proportionality with output swings and equalizer coefficients. Fabricated in 65 nm Digital CMOS process, the transmitter transmits a maximum of 1 V peak-to-peak differential output swing. In full-duplex mode, the transmitter equalizes 2 m UTP cable and dissipates 37.3 mW at 3Gb/s with echo canceller in the receiver path. The power reduces to 18.3 mW while transmitting across a 9 m UTP cable in the half-duplex mode.

35 km amplifier-less four-level pulse amplitude modulation signals enabled by a 23 GHz ultrabroadband directly modulated laser

The 4-level pulse amplitude modulation (PAM4) based on an 23 GHz ultrabroadband directly modulated laser (DML) was proposed. We have experimentally demonstrated that based on intensity modulation and direct detection (IMDD) 56 Gbps per wavelength PAM4 signals transferred over 35 km standard single mode fiber (SSMF) without any optical amplification and we have achieved the bit error rate (BER) of the PAM4 transmission was under 2.9 × 10−4 by using feed forward equalization (FFE).

DFE Error Propagation and FEC Interleaving for 400GbE PAM4 Electrical Lane

This paper analyzes the effect of error propagation of decision feedback equalizer (DFE) for PAM4 based 400Gb/s Ethernet. First, an analytic model for the error propagation is proposed to estimate the probability of different burst error length due to error propagation for PAM4 link system with multi-tap TX FFE (Feed Forward Equalizer) + RX DFE architecture. After calculating the symbol error rate (SER) and bit error rate (BER) based on the probability model, the theoretical analysis about the impact of different equalizer configurations on BER is compared with the simulation results, and then BER performance with FEC (Forward Error Correction) is analyzed to evaluate the effect of DFE error propagation on PAM4 link. Finally, two FEC interleaving schemes, symbol and bit interleaving, are employed in order to reduce BER further and then the theoretical analysis and the simulation result of their performance improvement are also evaluated. Simulation results show that at most 0.52dB interleaving gain can be achieved compared with non-interleaving scheme just at a little cost in storing memory and latency. And between the two interleaving methods, symbol interleaving performs better compared with the other one from the view of tradeoff between the interleaving gain and the cost and can be applied for 400Gb/s Ethernet.

Experimental Demonstration of 600 Gb/s Net Rate PAM4 Transmissions over 2 km and 10 km with a 4-λ CWDM TOSA

We propose to introduce a controlled amount of inter-symbol interference (ISI) during pulse shaping in a high symbol rate intensity modulation direct detection (IM/DD) system to increase the alternating current (AC) power of the received electrical signal after photo-detection and transimpedance amplification. We experimentally demonstrate high-speed 4-level pulse amplitude modulation (PAM4) transmissions with a 4-λ coarse wavelength division multiplexing (CWDM) transmitter optical sub-assembly (TOSA) using the proposed scheme. The intentionally introduced ISI is mitigated using either transmitter-side Tomlinson Harashima precoding (THP) or receiver-side feed forward equalization (FFE) aided with a 2-tap post filter and maximum likelihood sequence estimation (MLSE). Both methods enable 4 × 81 Gbaud PAM4 transmission over 2 km of single mode fiber (SMF), with a bit error rate (BER) below the 7% overhead hard-decision forward error correction (HD-FEC) threshold of 3.8 × 10−3, which corresponds to a net rate of >600 Gb/s. We also explore the limit of our system at 10 km. The result shows that an aggregated net rate of 600 Gb/s excluding the HD-FEC overhead can still be achieved by loading different symbol rates onto different wavelength channels.

Adaptive Equalization for Dispersion Mitigation in Multi-Channel Optical Communication Networks

Optical communication networks (OCNs) provide promising and cost-effective support for the ultra-fast broadband solutions, thus enabling them to address the ever growing demands of telecommunication industry such as high capacity and end users’ data rate. OCNs are used in both wired and wireless access networks as they offer many advantages over conventional copper wire transmission such as low power consumption, low cost, ultra-high bandwidth, and high transmission rates. Channel effects caused by light propagation through the fiber limits the performance, hence the data rate of the overall transmission. To achieve the maximum performance gain in terms of transmission rate through the OCN, an optical downlink system is investigated in this paper using feed forward equalizer (FFE) along with decision feedback equalizer (DFE). The simulation results show that the proposed technique plays a key role in dispersion mitigation in multi-channel optical transmission to uphold multi-Gb/s transmission. Moreover, bit error rate (BER) and quality factor (Q-factor) below 10 − 5 and above 5, respectively, are achieved with electrical domain equalizers for the OCN in the presence of multiple distortion effects showing the effectiveness of the proposed adaptive equalization techniques.

A gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade

This paper presents the design and simulation results of a gigabit transceiver Application Specific Integrated Circuit (ASIC) called GBCR for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR has four upstream receiver channels and a downstream transmitter channel. Each upstream channel operates at 5.12 Gbps, while the downstream channel operates at 2.56 Gbps. In each upstream channel, GBCR equalizes a signal received through a 5-meter 34-American Wire Gauge (AWG) twin-axial cable, retimes the data with a recovered clock, and drives an optical transmitter. In the downstream channel, GBCR receives the data from an optical receiver and drives the same type of cable as the upstream channels. The output jitter of an upstream channel is 26.5 ps and the jitter of the downstream channel after the cable is 33.5 ps. Each upstream channel consumes 78 mW and each downstream channel consumes 27 mW. Simulation results of the upstream test channel suggest that a significant jitter reduction could be achieved with minimally increased power consumption by using a Feed Forward Equalizer (FFE) + Decision Feedback Equalization (DFE) in addition to the linear equalization of the baseline channel. GBCR is designed in a 65-nm CMOS technology.

Demonstration of symmetrical 50-Gb/s TDM-PON in O-band supporting over 33-dB link budget with OLT-side amplification.

Single wavelength 50 Gb/s passive optical network (PON) is an excellent candidate for meeting high capacity requirements. In this paper, we experimentally investigate a symmetrical 50 Gb/s time division multiplexed passive optical network (TDM-PON) system in the O-band based on 25G optics. Semiconductor optical amplifier (SOA) is used in optical line terminal (OLT) side to improve link power budget. We initially investigate the performances of SOA as a booster amplifier with different gain in the downstream and make a trade-off between receiver sensitivity and power budget. The performances of 50 Gb/s non-return-to-zero (NRZ) in the downstream with avalanche photodiode (APD) receiver and upstream with SOA-PIN receiver with different equalization schemes are evaluated. Experimental results show that up to 34.97 dB link power budget is achieved in the downstream direction with 7-tap feed forward equalization (FFE), and 33.76 dB link power budget is achieved in the upstream direction with only 3-tap FFE filtering.

A Fully Adaptive 19–58-Gb/s PAM-4 and 9.5–29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET

The design of a dual-mode, 19-58-Gb/s four-level pulse-amplitude modulation (PAM-4) and 9.5-29-Gb/s nonreturn to zero (NRZ), transceiver in 16-nm FinFET is presented. The fully adaptive receiver consists of a multi-stage continuous time linear equalizer (CTLE), a configurable 32-way time-interleaved 3-to-7-bit successive-approximation-register (SAR) analog to digital converter (ADC), a 14-tap feed forward equalizer (FFE)/one-tap decision feedback equalizer (DFE) digital signal processing (DSP), and a baud-rate clock and data recovery (CDR). A four-tap voltage mode transmitter with two pre-cursor taps and one post-cursor tap, incorporates impedance control loop to meet return loss requirements while maintaining good PAM-4 level mismatch ratio of 0.98. At 56 Gb/s, the transceiver achieves the <;1e-12 bit error rate (BER) without explicitly added crosstalk, <;1e-6 BER with 2 mVrms (crest-factor of 10) additional crosstalk, over a 32-dB channel while consuming 9.7 pJ/bit with 7-bit ADC. The transceiver equalizes channel losses up to 46 dB with pre-forward error correction BER <;1e-5 at 58 Gb/s without additional crosstalk. With 3-bit ADC, it achieves 6.4 pJ/bit over a clean 7.4-dB channel.

Advanced Digital Signal Processing for Reach Extension and Performance Enhancement of 112 Gbps and Beyond Direct Detected DML-Based Transmission

112 Gbps per wavelength, amplification free Four-level Pulse Amplitude Modulation (PAM-4) transmissions are experimentally demonstrated with advanced digital signal processing (DSP) algorithms. Two DSP architectures are investigated for Directly Modulated Lasers (DMLs): 1) the regular DSP with Feed Forward Equalization (FFE) and Decision Feedback Equalization (DFE), and 2) the enhanced DSP with Maximum Likelihood Sequence Estimation (MLSE) equalizer. The experimental results show that with advanced DSP technologies the conventional DML can achieve 40 km transmissions with Bit Error Rate (BER) under 2.4 × 10−4 that meets RS (544, 514) Forward Error Correction (FEC) requirement; with regular-DSP the advanced DML can achieve 40 km transmissions with BER under 3.8 × 10−3, with stronger FEC. 112 Gbps and beyond per lambda DML based transmission is a promising low power, low-cost solution for 800 GbE or 1.6 TbE Ethernet.

60 Gbps 4-PAM VCSEL-based Raman assisted hyper-scale data centre: In context of spectral efficiency and reach extension

Abstract Cost effective large-scale installation of hyper-scale data centres has attracted extensive research recently, due to the exponential bandwidth demand over extended reach. Low cost, power and spectral efficient techniques for increasing network capacity, as well as extending the transmission reach while maintaining duplex connectivity are still key challenges facing current big data networks such as hyper-scale data centre networks. In this work, a low cost energy efficient technique for maximizing carrier spectral efficiency and extending transmission reach is experimentally demonstrated. This is achieved through combined adoption of vertical cavity surface emitting lasers (VCSELs), four level pulse amplitude modulation (4-PAM), dense wavelength division multiplexing (DWDM) and Raman amplification. Three class 10 G VCSEL channels are directly modulated with a 20 Gbps 4-PAM data signal therefore maximizing carrier spectral efficiency by doubling the data rate per channel. The channels are then converged to a single fibre link through DWDM technique at 0.4 nm spacing, achieving a total aggregated data rate of 60 (3 × 20) Gbps. By exploiting the 8.6 dB flat gain of a forward Raman pump, a 77.12 km of standard single mode fibre (SMF) transmission is experimentally achieved. To the best of our knowledge, this is the longest error free fibre transmission distance reported using VCSEL-based 60 Gbps 4-PAM, without any forward error correction (FEC), equalization and pre-emphasis mechanisms. Results show that a real time uncorrected BER

First demonstration of a 400 Gb/s 4λ CWDM TOSA for datacenter optical interconnects.

We present the first demonstration of a 4λ transmitter optical sub-assembly (TOSA) on the coarse wavelength division multiplexing (CWDM) grid, i.e., 20 nm spacing, targeting 400G-FR4 requirements over 2 km. The TOSA is based on uncooled InP external modulated laser (EML) technology and it utilizes four EMLs followed by a CWDM multiplexer. We characterize the performance of the TOSA versus received optical modulation amplitude (OMA), number of equalizer taps, reach, modulation format, TOSA case temperature, and bit rate. Four 53 Gbaud 4-level pulse amplitude modulation (PAM4) RF signals are used to drive the TOSA achieving a net rate of 400 Gb/s. Results reveal that 400 Gb/s can be transmitted over 2 km of single mode fiber (SMF) at a bit error rate (BER) below the KP4- forward error correction (KP4-FEC) threshold (i.e., 2.4 × 10-4) using only a 5 tap feed forward equalizer at the receiver. To the best of our knowledge, this is the first demonstration of 400 Gb/s using a 4λ CWDM TOSA over 2 km of SMF. Moreover, we achieve 400 Gb/s and 600 Gb/s over 20 km and 10 km below KP4-FEC and the 7% hard-decision FEC (HD-FEC) (i.e., 3.8 × 10-3) thresholds, respectively, without optical amplification. Furthermore, we show the performance of the TOSA against temperature, where it shows no significant change in the BER performance from 20 °C to 60 °C. Finally, we compare the performance of PAM2, PAM4, and PAM8 modulation formats where we show the possibility of achieving 400 Gb/s aggregate bit rate using 42 Gbaud PAM8 modulation format at the expense of utilizing a stronger FEC.

A 26-Gb/s 0.31-pJ/bit Receiver With Linear Sampling Phase Detector for Data and Edge Equalization

A source-synchronous receiver with a quarter-rate linear sampling phase detector (LSPD) using an embedded feed forward equalizer (FFE) and decision feedback equalizer (DFE) is proposed for chip-to-chip/module-to-module communication with medium channel loss. The quarter-rate LSPD is proposed to save power and avoid dithering jitter in a nonlinear bang-bang phase detector. To relax the timing constraint and improve the jitter performance of the recovered clock, a 1-tap FFE and a 1-tap DFE are applied to both the data path and the edge path so as to cancel the first and second post-cursors by reusing the linear samples. A charge-steering technique is adopted in the equalizer summer to minimize the power overhead. The receiver IC is fabricated in a 28-nm CMOS process and achieves error-free operation up to 26 Gb/s with a superior bit efficiency of 0.31 pJ/b while tolerating a 14-dB channel loss at 13 GHz.

Low-power, low-latency transceiver design using d-TGMS flip-flop for on-chip interconnects

The routers in Network on Chips (NoCs) are used to transmit the data among the Processing Elements (PEs) in the field, and it can be done through transmission links between the routers. Traditionally, the data transmission between the PEs of NoC is carried out by the parallel bus which consumes more power, leads to be complex routing strategies and occupies more area within the field. Instead of parallel bus, serializes and deserialisers are used for serial data transmission, which consumes very less power and area than traditional method. To implement serialiser-deserialiser at the transceiver in the router for on chip communication, a three-level encoding technique is implemented in this design, which eliminates power hungry blocks in earlier works, such as Phase Locked Loops, Feed Forward Equalizers, Decision Feedback Equalizers and the repeaters along the transmission line. In this paper, a low-power transceiver is proposed using modified C2MOS flip flop and Dynamic TGMS flip flop circuits in order to minimize the delay. The power reduction of 35.683% and the delay reduction of 44.71% were achieved in the proposed transceiver than the NAND gate based D flip flop transceivers.

Sparse Volterra model based on optical single side-band NPAM-4 direct-detection system

Abstract Signal-to-signal beating interference (SSBI) is one of the main drawbacks in direct-detection based optical transmission systems. Volterra filter is a common equalization method to mitigate the nonlinear distortion. However, the computational complexity may be unacceptable as the transmission capacity increases. In this paper, we propose a sparse Volterra model combining the feed forward equalization (FFE) and higher order terms of a modified Volterra filter with Schmidt orthogonal searching to mitigate the linear and nonlinear interference and reduce the complexity significantly in an optical single-side band (SSB) Nyquist pulse-shaped four-level pulse amplitude (NPAM-4) system. The experimental results show that the sparse Volterra filter and full Volterra filter have comparable performance, but the former only needs half kernels of the latter.