Forming Gas Annealing Research Articles

Anomalous Seebeck coefficient observed in silicon nanowire micro thermoelectric generator

We have found experimentally an anomalous thermoelectric characteristic of an n-type Si nanowire micro thermoelectric generator (μTEG). The μTEG is fabricated on a silicon-on-insulator wafer by electron beam lithography and dry etching, and its surface is covered with a thermally grown silicon dioxide film. The observed thermoelectric current is opposite to what is expected from the Seebeck coefficient of n-type Si. The result is understandable by considering a potential barrier in the nanowire. Upon the application of the temperature gradient across the nanowire, the potential barrier impedes the diffusion of thermally activated majority carriers into the nanowire, and it rather stimulates the injection of thermally generated minority carriers. The most plausible origin of the potential barrier is negative charges trapped at the interface between the Si nanowire and the oxide film. We practically confirmed that the normal Seebeck coefficient of the n-type Si nanowire is recovered after the hydrogen forming gas annealing. This implies that the interface traps are diminished by the hydrogen termination of bonding defects. The present results show the importance of the surface inactivation treatment of μTEGs to suppress the potential barrier and unfavorable contribution of minority carriers.

Examining the relationship between capacitance-voltage hysteresis and accumulation frequency dispersion in InGaAs metal-oxide-semiconductor structures based on the response to post-metal annealing

In this work, we investigated the effect of forming gas annealing (FGA, 5% H2/95% N2, 250°C to 450°C) on border trap density in high-k/InGaAs metal-oxide-semiconductor (MOS) systems using accumulation frequency dispersion and capacitance-voltage (CV) hysteresis analysis. It is demonstrated that the optimum FGA temperature that reduces the accumulation frequency dispersion is 350°C for HfO2/n-InGaAs and 450°C for Al2O3/n-InGaAs MOS system. Volume density of border traps (Nbt) is estimated using the accumulation frequency dispersion based on a distributed model for border traps. It is shown that for HfO2/n-InGaAs MOS system, Nbt is reduced from 9.4×1019cm−3eV−1 before FGA to 6.3×1019cm−3eV−1 following FGA at 350°C. For the case of Al2O3/n-InGaAs MOS system, Nbt is reduced from 5.7×1019cm−3eV−1 for no FGA to 3.4×1019cm−3eV−1 for FGA at 450°C. Furthermore, it is shown that the most pronounced reduction in border trap density estimated from CV hysteresis analysis is observed at the same optimum FGA temperature that reduces the accumulation frequency dispersion, indicating that these two techniques for border trap analysis are correlated.

Single electron transistors with hydrogen treatment of ALD SiO2 in nanoscale metal–insulator–metal tunnel junctions

Over the past five years, fabrication of metal–insulator–metal (MIM) single electron transistors (SET) featuring atomic layer deposition (ALD) of ultrathin tunnel barrier dielectrics (SiO2, Al2O3) has been reported. However, the performance of fabricated devices was significantly compromised by the presence of native metal oxide and problems associated with the nucleation of ALD dielectrics on metal substrates. To overcome the difficulty of dielectric ALD nucleation on metal substrates, we recently developed a fabrication technique in which the native metal oxide naturally forming in the presence of the ALD oxidant precursor is first used to promote the nucleation of ALD dielectrics, and then is chemically reduced by forming gas anneal (FGA) at temperatures near 400 °C. However, despite the elimination of native oxide, low temperature characterization of the devices fabricated using FGA reveals excess ‘switching’ noise of a very large magnitude resulting from charged defects within the junctions. It has been previously reported that remote hydrogen plasma (RHP) treatment of SiO2 thin films effectively eradicates fabrication defects. This work reports a comparative study of Ni-based MIM SET treated with FGA and/or RHP. We show that, using a combination of FGA and RHP treatments, it is possible to obtain MIM junctions free of switching noise and without a detectable contribution of native oxide.

Improved indium oxide transparent conductive thin films by hydrogen annealing

In2O3 thin films were prepared by reactive evaporation with post-annealing treatment at forming gas of N2 and H2. After post-annealing treatment, the films annealed at forming gas achieved lowest resistivity of 2.70×10−4Ωcm. The XRD results show that the In2O3 films annealed in forming gas and N2 with good recrystallization. In the forming gas annealing process, hydrogen plays a key role in the generation of oxygen vacancies and enhances the formation of In–OH bond which may influence the electrical and optical properties of the In2O3 films.

The impact of forming gas annealing on the electrical characteristics of sulfur passivated Al2O3/In0.53Ga0.47As (110) metal-oxide-semiconductor capacitors

This study reports the impact of forming gas annealing (FGA) on the electrical characteristics of sulfur passivated, atomic layer deposited Al2O3 gate dielectrics deposited on (110) oriented n- and p-doped In0.53Ga0.47 As layers metal-oxide-semiconductor capacitors (MOSCAPs). In combination, these approaches enable significant Fermi level movement through the bandgap of both n- and p-doped In0.53Ga0.47 As (110) MOSCAPs. A midgap interface trap density (Dit) value in the range 0.87−1.8×1012 cm−2eV−1 is observed from the samples studied. Close to the conduction band edge, a Dit value of 3.1×1011 cm−2eV−1 is obtained. These data indicate the combination of sulfur pre-treatment and FGA is advantageous in passivating trap states in the upper half of the bandgap of (110) oriented In0.53Ga0.47 As. This is further demonstrated by a reduction in border trap density in the n-type In0.53Ga0.47 As (110) MOSCAPs from 1.8×1012 cm−2 to 5.3×1011 cm−2 as a result of the FGA process. This is in contrast to the observed increase in border trap density after FGA from 7.3×1011 cm−2 to 1.4×1012 cm−2 in p-type In0.53Ga0.47 As (110) MOSCAPs, which suggest FGA is not as effective in passsivating states close to the valence band edge.

A 14.7% Organic/Silicon Nanoholes Hybrid Solar Cell via Interfacial Engineering by Solution-Processed Inorganic Conformal Layer.

We demonstrated a high-performance Si-organic hybrid heterojunction solar cell utilizing low-temperature and liquid-phase-processed TiO2 as an interlayer between poly(3,4-ethylene dioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) and Si nanoholes to produce a conformal contact on the surface of the Si nanostructure. The hydrophilic TiO2/Si-nanohole surface enabled the PEDOT:PSS to flow into the spacing of the close-packed nanoholes. Scanning electron microscopy images were used to confirm the PEDOT:PSS nanohole filling induced by the TiO2. With forming gas annealing of the double-sided TiO2, high Voc (0.63 V) and Jsc (35.7 mA/cm2) values were obtained, yielding a high power conversion efficiency of 14.7%. The high Voc was attributed to the surface passivation of Si by annealed TiO2. The X-ray photoelectron spectroscopy investigation at the TiO2/Si interface indicates the TiOx signal decreased and the TiO2 and SiOx signals increased after annealing. The Si-O bonding found in the O 1s study appeared in the form of Si-O-Si bonding to serve surface passivation. The band alignment of the PEDOT:PSS/TiO2/n-Si hetero-interfaces was postulated and plotted. The Vbi in the system after annealing was assumed to be higher because of the reduction of bulk and surface states that yield high Voc. After annealing, the Vbi increased from 0.805 to 0.905 V. The reduction of surface recombination velocity proved the passivation ability of TiO2 after annealing. With proven surface passivation and conformal PEDOT:PSS/Si nanohole interfaces for enhanced contact, this Si-organic hybrid heterojunction solar cell with solution-processed TiO2 interlayers has excellent potential for application as a high-efficiency and low-cost Si solar cell.

Systematic study of interfacial reactions induced by metal electrodes in high-k/InGaAs gate stacks

We systematically studied the effects of metal electrodes on high-k/InGaAs gate stacks and observed that the remote reactions—both oxidation and reduction—at the interface between the high-k dielectrics and InGaAs were thermodynamically initiated by the metal electrodes. Metal electrodes with negative Gibbs free energies (e.g., Pd) resulted in the oxidation of the InGaAs surface during the forming-gas annealing. In contrast, with TiN electrodes, which have a positive Gibbs free energy, the native III–V oxides underwent the reduction between the high-k dielectrics and InGaAs. We demonstrated that the reduction of native III–V oxides by metal electrodes improved the interface quality of the high-k/InGaAs gate stacks and produced an interface trap density (Dit) at the mid-gap with a value as low as 5.2 × 1011 cm−2 eV−1 with a scaled capacitance-equivalent thickness.

Interface Characterization of HfO2/GaSb MOS Capacitors With Ultrathin Equivalent Oxide Thickness by Using Hydrogen Plasma Treatment

We investigate p-type GaSb MOS capacitors with various HfO2 thicknesses grown using an atomic layer deposition. GaSb surfaces treated with ex-situ chemical solution and in situ remote hydrogen plasma are inspected. After a series of etching steps, the GaSb surfaces exhibit smooth topography, indicating that this combination of treatments is capable of realizing ultrathin dielectric deposition. After etching processes, the ultrathin (approximately 3 nm) HfO2 layer deposited successfully on GaSb exhibit high-permittivity (approximately 21) properties as well as equivalent oxide thickness (EOT) of 0.75 nm, which can be attributed to the flat surface. To the best of our knowledge, the EOT of GaSb capacitor prepared using the exploited approach is record low. Furthermore, we find that the interlayer present after hydrogen plasma treatment and forming gas annealing could efficiently passivate interface state density and achieve high $C$ – $V$ modulation. Compared with the benchmark of gate leakage current versus EOT, the electrical performance with low gate leakage current of the GaSb MOS capacitors demonstrates the high feasibility of the proposed treatments.

Passivating electron contact based on highly crystalline nanostructured silicon oxide layers for silicon solar cells

We present a novel passivating contact structure based on a nanostructured silicon-based layer. Traditional poly-Si junctions feature excellent junction characteristics but their optical absorption induces current losses when applied to the solar cell front side. Targeting enhanced transparency, the poly-Si layer is replaced with a mixed-phase silicon oxide/silicon layer. This mixed-phase layer consists of an amorphous SiOx matrix with incorporated Si filaments connecting one side of the layer to the other, and is referred to as nanocrystalline silicon oxide (nc-SiOx) layer. We investigate passivation quality, measured as saturation current density, and nanostructural changes, characterized by Raman spectroscopy and transmission electron microscopy, carefully studying the influence of annealing dwell temperature. Excellent surface passivation on n-type and also p-type wafers is shown. An optimum annealing temperature of 950°C is found, resulting in a saturation current density of 8.8fAcm−2 and 11.0fAcm−2 for n-type and p-type wafers, respectively. Even before forming gas annealing, emitter saturation current densities of 27.9 fA cm−2 (n+/n junction) and 32.0 fA cm−2 (n+/p junction) are reached. Efficient current extraction is presented with specific contact resistivities of 86mΩcm2 on n-type wafer and 19mΩcm2 on p-type wafers, respectively. High-resolution transmission electron microscopy reveals that the layer stack consists of intermixed SiOx and Si phases with the Si phases being partly crystalline already in the as-deposited state. Thermal annealing at temperatures ≥850°C further promotes crystallization of the Si-rich regions. The addition of the SiOx phase enhances the thermal stability of the contact and should allow to tune the refractive index and improve transparency, while still providing efficient electrical transport through the crystalline Si phase, which extends throughout almost the entire contact.

Ultra-thin silicon oxide layers on crystalline silicon wafers: Comparison of advanced oxidation techniques with respect to chemically abrupt SiO2/Si interfaces with low defect densities

Six advanced oxidation techniques were analyzed, evaluated and compared with respect to the preparation of high-quality ultra-thin oxide layers on crystalline silicon. The resulting electronic and chemical SiO2/Si interface properties were determined by a combined x-ray photoemission (XPS) and surface photovoltage (SPV) investigation. Depending on the oxidation technique, chemically abrupt SiO2/Si interfaces with low densities of interface states were fabricated on c-Si either at low temperatures, at short times, or in wet-chemical environment, resulting in each case in excellent interface passivation. Moreover, the beneficial effect of a subsequent forming gas annealing (FGA) step for the passivation of the SiO2/Si interface of ultra-thin oxide layers has been proven. Chemically abrupt SiO2/Si interfaces have been shown to generate less interface defect states.

Investigation of the Interface Quality and Reliability of 4H-SiC MOS Structure with NO and Forming Gas Annealing Treatment

Effects of NO and forming gas annealing treatment on the interface quality and reliability of 4H-SiC MOS were systematically studied by low temperature conductance measurements in combination with time-zero dielectric breakdown and time-dependent dielectric breakdown methods. The interface trap density (Dit) showed no obvious reduction after forming gas annealing, and the values of Dit decreased significantly after combined NO and forming gas annealing treatment. The F-N barrier height, electric field to breakdown (Ebd) and charge to breakdown (Qbd) of the MOS structure increased from 2.42 eV, 10 MV/cm, 1mC/cm2 to 2.62 eV, 10.7 MV/cm, 78mC/cm2 after forming gas annealing. The values of F-N barrier height, Ebd and Qbd for MOS capacitors with combined NO and forming gas annealing treatment are 2.69 eV, 10.2 MV/cm, and 24mC/cm2. These results suggest that forming gas annealing is more effective in reliability improvement. While when considering the interface trap density, it seems that combined NO and forming gas annealing treatment is a better choice.

Passivation of Al2O3 / TiO2 on monocrystalline Si with relatively low reflectance

Al2O3/TiO2 stack layers deposited by the plasma-enhanced atomic layer deposition enhance photoluminescence intensity by reducing effective surface recombination velocities on both n-type and p-type monocrystalline Si. The field effect of negative oxide charges in the dielectrics is responsible for the low effective surface recombination velocity. The dependence of the effective surface recombination velocity on the photoluminescence intensity is investigated by the 2D numerical simulation. The bilayer stacks without texture also reduce the AM1.5-weighted front side reflectance to 11.8%. The field-effect passivation of Al2O3/TiO2 films is further improved by a forming gas annealing due to the additional increase of the negative oxide charge density.

Comparison between Si/SiO2 mid‐gap interface states and deep levels associated with silicon‐oxygen superlattices in p‐type silicon

AbstractIn this paper, the deep levels found by deep‐level transient spectroscopy in Si‐O superlattices on p‐type silicon substrates are compared with the band of near mid‐gap hole traps typically observed at the Si/SiO2 interface. In addition, the impact of a post‐deposition Forming Gas Annealing is investigated. A large similarity between the two material systems is reported, which indicates that similar silicon‐oxygen bonds may be responsible for the deep hole traps.(© 2016 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Impact of hydrogen forming gas annealing on microwave properties of Ba(Zn1/3Ta2/3)O3 dielectric ceramics

The effect of H2forming gas annealing on the microwave properties of [Formula: see text] (BZT) dielectric ceramics has been studied. The structural, microwave, DC electrical and optical properties were analyzed by experiment results. With elevated temperature annealing, the microwave loss of BZT was increased. This trend correlated with high DC conductivity of annealed samples, as well as dampened phonons found in Raman spectra. These evidences, together, prove that the enhancement of oxygen vacancy defects induced by oxygen deficient sintering environment is one of the main extrinsic root causes for the high microwave loss in practical ceramic materials.

Experimental study on interface region of two-dimensional Si layers by forming gas annealing

We experimentally studied the SiO2/Si and Si/buried oxide (BOX) interface regions of a two-dimensional (2D) Si layer, by forming gas annealing (FGA). A photoluminescence (PL) result measured at various lattice temperature, TL, values shows that the PL intensity IPL of the 2D-Si layer rapidly increases and then saturates with increasing FGA temperature, TA, and time, tA. IPL also increases with decreasing TL. A one-dimensional (1D) Schroedinger equation simulator indicates that some of the electrons in the 2D-Si layer generated by a PL excitation laser are quantum–mechanically transmitted into Si interface regions. Actually, we experimentally confirmed that the PL spectra of the 2D-Si layer can be fitted by the PL emission from two regions with different PL peak photon energy values, EPH, which consist of a typical 2D-Si and the interface regions of both the surface SiO2/Si and Si/BOX. Thus, this forming gas dependence is probably attributable to the improved lifetime τ of electrons in the surface interface region, because the Si surface is terminated by H atoms. Moreover, the EPH of the interface region is higher than that of the 2D-Si layer, because of the graded increased bandgap in the interface regions. However, the EPH of 2D-Si is independent of both TA and TL, and this TL independence does not agree with that of a 3D-Si layer. Consequently, we experimentally verified the larger impact of the Si interface on the performance of 2D-Si layer.

Interface properties of Al–Al2O3–Ge MIS capacitors and the effect of forming gas annealing

In this work the effect of Al deposition process and the subsequent forming gas annealing on the interfacial properties of Al/Al2O3/p-Ge MOS capacitors is studied. Al2O3 has been deposited by ALD at 300°C. There is evidence that Al deposition by e-beam evaporation affects the structure and composition of the Al2O3/Ge interface by decomposing the GeOx interfacial layer and leading to interfacial non-uniformities reflected in conductance measurements. Forming gas annealing is able to passivate interface traps near the valence band edge possibly originating from Al2O3–Ge dangling bonds during the dielectric deposition. However it is unable to passivate interface traps near the midgap possibly originating from e-beam evaporation radiation damage.

Characterization of the effects of nitrogen and hydrogen passivation on SiO2/4H-SiC interface by low temperature conductance measurements**Project supported by the National Natural Science Foundation of China (Nos. 61106080, 61275042) and the National Science and Technology Major Project of the Ministry of Science and Technology of China (No. 2013ZX02305).

We investigate the effects of NO annealing and forming gas (FG) annealing on the electrical properties of a SiO2/SiC interface by low-temperature conductance measurements. With nitrogen passivation, the density of interface states (DIT) is significantly reduced in the entire energy range, and the shift of flatband voltage, ΔVFB, is effectively suppressed to less than 0.4 V. However, very fast states are observed after NO annealing and the response frequencies are higher than 1 MHz at room temperature. After additional FG annealing, the DIT and ΔVFB are further reduced. The values of the DIT decrease to less than 1011 cm−2 eV−1 for the energy range of EC − ET > 0.4 eV. It is suggested that the fast states in shallow energy levels originated from the N atoms accumulating at the interface by NO annealing. Though FG annealing has a limited effect on these shallow traps, hydrogen can terminate the residual Si and C dangling bonds corresponding to traps at deep energy levels and improve the interface quality further. It is indicated that NO annealing in conjunction with FG annealing will be a better post-oxidation process method for high performance SiC MOSFETs.

Amorphous layers by electron beam evaporator deposition for hetero-junction with intrinsic thin layer solar cells applications

A low-cost process with electron beam evaporator deposition for amorphous layers was demonstrated in hetero-junction with intrinsic thin layer (HIT) solar cell. The cleaning process with saw damage removal procedure and the annealing temperature are also discussed in this work. The open-circuit voltage (Voc) and short-circuit current density (Jsc) were obtained as 285 mV and 2.9 mA/cm², respectively, with 5 min saw damage removal and 450°C forming gas annealing. Therefore, the low-cost process with the electron beam evaporator deposition could possibly fabricate the HIT solar cell and be a candidate for future higher performance photovoltaic device with optimisation process condition.

Effects of combined NO and forming gas annealing on interfacial properties and oxide reliability of 4H-SiC MOS structures

The effects of NO and forming gas post oxidation annealing treatments on the interfacial properties and reliability of thermal oxides grown on n-type 4H-SiC (0001) Si face have been investigated in this study. The results show that forming gas annealing (FGA) treatment has limited effect on interface trap density (Dit) while it results in an improvement of the insulating properties of thermal oxide with uniform high FN barrier height (2.56eV), high field-to-breakdown (10.71 MV/cm) and charge-to-breakdown (0.078 C/cm2). On the other hand, NO annealing causes a drastic reduction in Dit in the entire energy level, but in the case of reliability, it is not so effective as FGA, with lower barrier height (2.52eV), field-to-breakdown (10.08 MV/cm), charge-to-breakdown (0.025 C/cm2) and worse uniformity of oxide. The combined NO&FGA treatment was also studied. It leads to a significant reduction in interface trap density further, especially in deep energy level (EC-ET≥0.4eV). As for reliability, it brings about uniform barrier height (2.69eV), field-to-breakdown (10.15 MV/cm) and charge-to-breakdown (0.024 C/cm2). Taking interfacial properties and reliability into account, combined NO&FGA treatment is a promising POA technique for fabrication of high-quality SiC MOS devices.

Border trap reduction in Al2O3/InGaAs gate stacks

The effect of Al2O3 atomic layer deposition (ALD) temperature on the border trap density (Nbt) of Al2O3/InGaAs gate stacks is investigated quantitatively, and we demonstrate that lowering the trimethylaluminum (TMA)/water vapor ALD temperature from 270 °C to 120 °C significantly reduces Nbt. The reduction of Nbt coincides with increased hydrogen incorporation in low temperature ALD-grown Al2O3 films during post-gate metal forming gas annealing. It is also found that large-dose (∼6000 L) exposure of the In0.53Ga0.47As (100) surface to TMA immediately after thermal desorption of a protective As2 capping layer is an important step to guarantee the uniformity and reproducibility of high quality Al2O3/InGaAs samples made at low ALD temperatures.