Process Parameter Fluctuations Research Articles

Analog IC Variability Bound Estimation Using the Cornish–Fisher Expansion

In nanoscale integrated circuit technologies, process parameter fluctuations gain increasingly in importance. Efficient methods are thus required during the design phase to evaluate the resulting variability. In this letter, we propose a new method to estimate the variation bounds of analog circuit performance. This method combines design of experiment techniques with the Cornish-Fisher expansion: process parameter variations are first mapped to circuit performance metrics by a quadratic model, and then an analytical approximation of the performance distribution's quantiles enables the enclosure of the performance variations. The proposed method demonstrates a better accuracy/efficiency ratio than Monte-Carlo-based methods.

Modeling of plasma-induced damage and its impacts on parameter variations in advanced electronic devices

A comprehensive model predicting the effects of plasma-induced damage (PID) on parameter variations in advanced metal–oxide–semiconductor field-effect transistors (MOSFETs) is proposed. The model focuses on the silicon recess structure (Si loss) in the source/drain extension region formed by high-energy ion bombardment during plasma etching. The model includes the following mechanisms: (1) damaged layer formation by ion impact and penetration, (2) Si recess structure formation by a subsequent wet etch, (3) MOSFET performance degradation, and (4) MOSFET parameter variation. Based on a range theory for plasma-etch damage, the thickness of the damaged layer exhibits a power-law dependence on the energy of the ion incident on the surface of Si substrate. Assuming that the damaged layer was formed during a gate or an offset spacer etch process, the depth of Si recess (dR) is a function of the depth profile of the created defect site (ndam), the wet-etch stripping time (tw), and the energy of the incident ion. It was found that dR also showed a power-law dependence on the average ion energy E−ion estimated from applied self-dc-bias voltage for various tw. As for MOSFET performance degradation, the threshold voltage (Vth) shifted and the shift (ΔVth) increased with an increase in E−ion and a decrease in gate length. This induces an increase in subthreshold leakage current (Ioff) for MOSFET. Technology computer-aided-design simulations were performed to confirm these results. By integrating the presented PID models, parameter variations could be predicted: Using a Monte Carlo method, it was demonstrated that PID increases parameter variations such as Vth and Ioff. It also was found that the variation in E−ion induces Vth and Ioff variations, comparable to that induced by other process parameter fluctuations such as dopant fluctuation and gate length. In summary, considering the effects of PID on parameter variations is vital for designing future ultralarge-scale-integrated circuits with billions of built-in MOSFETs.

Effects of process variation in VLSI interconnects – a technical review

PurposeProcess variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. The purpose of this paper is to provide a comprehensive overview of types and sources of all aspects of interconnect process variations.Design/methodology/approachThe impacts of these interconnect process variations on circuit delay and cross‐talk noises along with the two major sources of delays – parametric delay variations and global interconnect delays – have been discussed.FindingsParametric delay evaluation under process variation method avoids multiple parasitic extractions and multiple delay evaluations as is done in the traditional response surface method. This results in significant speedup. Furthermore, both systematic and random process variations have been contemplated. The systematic variations need to be experimentally modeled and calibrated while the random variations are inherent fluctuations in process parameters due to any reason in manufacturing and hence are non‐deterministic.Originality/valueThis paper usefully reviews process variation effects on very large‐scale integration (VLSI) interconnect.

Experiments on Water Detritiation and Cryogenic Distillation at TLK; Impact on ITER Fuel Cycle Subsystems Interfaces

The ITER Isotope Separation System (ISS) and Water Detritiation System (WDS) should be integrated in order to reduce potential chronic tritium emissions from the ISS. This is achieved by routing the top (protium) product from the ISS to a feed point near the bottom end of the WDS Liquid Phase Catalytic Exchange (LPCE) column. This provides an additional barrier against ISS emissions and should mitigate the memory effects due to process parameter fluctuations in the ISS. To support the research activities needed to characterize the performances of various components for WDS and ISS processes under various working conditions and configurations as needed for ITER design, an experimental facility called TRENTA representative of the ITER WDS and ISS protium separation column, has been commissioned and is in operation at TLK.The experimental program on TRENTA facility is conducted to provide the necessary design data related to the relevant ITER operating modes. The operation availability and performances of ISS-WDS have impact on ITER fuel cycle subsystems with consequences on the design integration. The preliminary experimental data on TRENTA facility are presented.

Advanced Annealing Schemes for High-Performance SOI Logic Technologies

We have extensively studied the impact of advanced annealing schemes for highperformance SOI logic technologies. Starting with the 130 nm technology node, we introduced spike rapid thermal annealing (sRTA). Continuous temperature reduction combined with implant scaling helped to improve transistor performance and short channel behavior. During the development of the 90 nm technology we evaluated flash lamp and laser annealing (FLA). These techniques became an essential part of the 65 nm node. At this node we also faced major challenges in terms of compatibility with new materials like SiGe as well as the need for reduction of process parameter fluctuations. Scaling will be continued with the 45 nm technology node towards a truly diffusionless process.

Commissioning of water detritiation and cryogenic distillation systems at TLK in view of ITER design

The ITER Isotope Separation System (ISS) and Water Detritiation System (WDS) will be integrated in order to reduce potential chronic tritium releases from the ISS by routing the top (protium) product from the ISS into the Liquid Phase Catalytic Exchange (LPCE) column of WDS. This provides an additional barrier against ISS tritium releases and should mitigate the memory effects due to process parameter fluctuations in the ISS. To support the research activities needed to characterize the performances of various components for WDS and ISS processes in various working conditions and configurations as needed for ITER design, an experimental facility called TRENTA and representative of the ITER WDS and ISS protium separation column has been commissioned at Tritium Laboratory Karlsruhe (TLK). The TRENTA facility consists of Combined Electrolysis Catalytic Exchange (CECE) process, with an LPCE column of 8 m, in combination with a cryogenic distillation (CD) process. The processes description and the status of commissioning of TRENTA facility is presented.

Reduced Parameter Fluctuation with Laser and Flash Lamp Anneal for 65nm Volume Production

Process parameter fluctuations have a strong impact on functionality and performance of CMOS logic circuits and memory cells. Tight control of transistor gate length and final anneal temperature are equally important. We have developed a strategy to monitor these fluctuations which takes into account the full complexity of advanced microprocessors with large cache cell areas. This paper shows that reducing the anneal temperature reduces the parameter fluctuations. Transistor performance degradation at reduced temperatures can be compensated by using advanced annealing techniques like Laser or Flash lamp anneal. These techniques do not result in additional parameter fluctuation.

CMOL: A Silicon-Based Bottom-Up Approach to Nanoelectronics

The current VLSI paradigm based on a combination of lithographic patterning, CMOS circuits, and Boolean logic (outlined in the first part of this article), can hardly be extended into a-few-nm region. The main reason is that at physical gate lengths below 10 nm, the sensitivity of parameters (most importantly, the gate voltage threshold) of silicon field-effect transistors to inevitable fluctuations in fabrication process parameters increases exponentially.

Structure and properties of AIMgSi1 alloy tailored for semi-solid forming

Thixoforming requires semi-solid slurries, which contain a high volume fraction of non-dendritic solid phase with special grain morphology. Volume fraction, geometry and connectivity of the solid α-phase has to be kept within narrow limits. The paper illustrates the development of a new aluminium based wrought alloy AIMgSi1 alloy, adapted with barium, characterised by a microstructure which exhibits a low sensitivity towards fluctuations in process parameters resulting in improved mechanical properties of the alloy. The rheological behaviour of the new alloy by means of backward extrusion experiments is described, and an overview of the static and dynamic strength properties is given that can be achieved when the alloy is processed by means of the New Rheocasting process.

Nonlinear variance model for analysis of effectsof process-parameter fluctuations

A nonlinear variance equation has been derived and applied to the threshold voltage of a 0.1 /spl mu/m SOI MOS device. The equation enabled an analysis of the effects of process-parameter fluctuations to be made. The analysis showed that the effect of the nonlinear terms (15.48%) is more important than the effect of the mixed term (0.02%), and almost as important as the contribution of the second most dominant input-process parameter (21.98%). This illustrates the importance of the proposed nonlinear equation.

A case study on process optimization using the gradient loss function

This paper focuses on studies where the goal is to optimize the key quality characteristics of a specific product or process. In order to do that, the process parameters must be adjusted in such a way that deviations from target are minimized while robustness to noise and to process parameter fluctuations are maximized. Since this is a multi-response, multi-objective problem, the optimum solution is a compromise. In this paper we present a gradient loss function which captures all the desired objectives, and propose a general methodology to perform the optimization analysis. This methodology is then carried out experimentally on a cosmetic product and the results are discussed.

Influence of process parameter variations on the signal distribution behavior of wafer scale integration devices

With decreasing geometries of MOS transistors in VLSI devices, the influence of fluctuations of process parameters during manufacturing will become more and more important, because process tolerances are not proportionally scaled to geometries. These fluctuations result in a performance spread of the devices produced by a certain process. For instance the clock rate of a microprocessor as a typical performance indicator, can vary in a wide range. One of the key issues of the implementation of circuits using wafer scale integration technologies is the synchronous distribution of signals, either clock, data or control over a large area of silicon. Fluctuations of process parameters can have a major influence on the performance of these devices. In the following paper, an efficient method for accurate prediction of the performance spread of integrated circuits is discussed and demonstrated by simulations. All the simulations are verified by measurements on a test-circuit with a huge number of test devices. The method is applied to different signal distribution networks of wafer scale integration devices to show the sensitivity of performance to these variations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A physical and computationally efficient methodology for statistical circuit simulation in bipolar technologies

A methodology for statistical circuit simulation in advanced bipolar technologies is developed based on a novel IC TCAD system consisting of the semi-numerical mixed-mode device/circuit simulator MMSPICE with its parameter evaluator SUMM. The system reliably and efficiently relates device/circuit performance directly to measurable fabrication-process parameters since MMSPICE/SUMM implicitly accounts for physical correlations among device model parameters and does not rely on optimization (i.e. parameter extraction). The computational efficiency permits use of a simple Monte Carlo technique involving random generation of process parameters for the statistical simulation. The utility of the methodology is demonstrated by predicting IC parametric yields and statistical device/circuit performance correlations from specified fluctuations of process parameters in an actual bipolar technology.

Compositional heterogeneity in polymers: computer simulation approaches

A family of computer programs (called PODIS) has been written that permits compositional heterogeneity in copolymers to be directly computed. Different sources of compositional heterogeneity have been specifically addressed by separate programs. Included in the treatments are statistical heterogeneity, conversion heterogeneity, multistate heterogeneity, and compositional heterogeneity due to fluctuations in polymerization process parameters. Through these means, predicted chemical composition distributions have been made for linear low-density polyethylene, styrene/ethyl methacrylate copolymers, and styrene/methyl acrylate copolymers

A general stochastic model for intermediate storage in noncontinuous processes

A significant role of intermediate storage in noncontinuous manufacturing systems is to decouple stages of operations. It eliminates delays and interruptions caused by the uncertainty in process operations, and increases the availability of the process. We present a stochastic model for intermediate storage in a two-stage process with multiple, nonidentical parallel units in each stage. In contrast to the existing models, the new model allows a simultaneous treatment or arbitrary types of random process disturbances such as operation (processing, cleaning, transfer, set-up etc.) time variations, unit failures and repairs, batch failures, batch size variations, etc. Using well-known results from the probability theory, we derive general analytical expressions for sizing intermediate storage to maintain the continuity of operation with a given degree of confidence. We apply these expressions to the two-stage system with only the process parameter fluctuations, and obtain specific results. For this process, we compare our model with the existing models and Monte Carlo simulation. The new model predicts much smaller storage sizes than the other models and compares very well with the simulation results.