Flow Graph Structure Research Articles

Fast Verification of Network Configuration Updates

With the expansion of network services, large-scale networks have progressively become common. The network status changes rapidly in response to customer needs and configuration changes, so network configuration changes are also very frequent. However, no matter what changes, the network must ensure the correct conditions, such as isolating tenants from each other or guaranteeing essential services. Once changes occur, it is necessary to verify the after-changed network. Whereas, for the verification of large-scale network configuration changes, many current verifiers show poor efficiency. In order to solve the problem of multiple global verifications caused by frequent updates of local configurations in large networks, we present a fast configuration updates verification tool, FastCUV, for distributed control planes. FastCUV aims to enhance the efficiency of distributed control plane verification for medium and large networks while ensuring correctness. This paper presents a method to determine the network range affected by the configuration change. We present a flow model and graph structure to facilitate the design of verification algorithms and speed up verification. Our scheme verifies the network area affected by obtaining the change of the Forwarding Information Base (FIB) before and after. FastCUV supports rich network attributes, meanwhile, has high efficiency and correctness performance. After experimental verification and result analysis, our method outperforms the state-of-the-art method to a certain extent.

Portable and platform-independent MR pulse sequence programs.

To introduce a new sequence description format for vendor-independent MR sequences that include all calculation logic portably. To introduce a new MRI sequence development approach which utilizes flexibly reusable modules. The proposed sequence description contains a sequence module hierarchy for loop and group logic, which is enhanced by a novel strategy for performing efficient parameter and pulse shape calculation. These calculations are powered by a flow graph structure. By using the flow graph, all calculations are performed with no redundancy and without requiring preprocessing. The generation of this interpretable structure is a separate step that combines MRI techniques while actively considering their context. The driver interface is slim and highly flexible through scripting support. The sequences do not require any vendor-specific compiling or processing step. A vendor-independent frontend for sequence configuration can be used. Tests that ensure physical feasibility of the sequence are integrated into the calculation logic. The framework was used to define a set of standard sequences. Resulting images were compared to respective images acquired with sequences provided by the device manufacturer. Images were acquired using a standard commercial MRI system. The approach produces configurable, vendor-independent sequences, whose configurability enables rapid prototyping. The transparent data structure simplifies the process of sharing reproducible sequences, modules, and techniques.

Basis Path Testing of Iterative Deepening Search and Held-Karp on Pathfinding Algorithm

This research is a continuation of previous research, where in previous research discussed about the implementation of both methods. Implementation is done using visual basic programming language. Both methods are compared based on the results obtained. While in the current study, research is more focused on the analysis of the program flow that has been made. Evaluation is done by using basis path method, there are several processes performed on the method, such as: flowgraph, independent path, cyclomatic complexity and graph matrix. In addition to the evaluation of program flow, evaluation is also done based on program performance. Performance tests are based, time, cpu and memory. Based on the evaluation using the base path, obtained flowgraph structure and independent path different, but obtained the result of CC and Graph Matrix calculation of the same between IDS and HK method is 4. Based on evaluation in terms of performance, process the program from entering data and until getting the result, the HK method takes a longer time than the IDS method. The IDS method takes 2.7 seconds while the HK method takes 2.8 seconds.

Signal Flow Graph Synthetical Implement the Current-Mode Multifunction Filter Based on CDTA

In this paper, a signal flow graph structure of current-mode multifunction filter using current differencing transconductance amplifier (CDTA) is presented. The proposed configuration is comprised of two grounded capacitors and four CDTAs. They exhibit low-input and high-output impedances, which is very convenient for integrated circuit implementation. The presented filter configuration can realize all the standard filter functions simultaneously, lowpass (LP), bandpass (BP), highpass (HP), bandstop (BS) and allpass (AP), without any component matching conditions. The natural frequency () and the bandwidth () of the proposed filter can be electronically tuned by varying the bias current of the CDTA. PSPICE simulation results are included to confirm the theory.

Perceptual Encryption of H.264 Videos: Embedding Sign-Flips Into the Integer-Based Transforms

An alternative-transforms-based scheme has recently been proposed to achieve perceptual encryption of video signals in which multiple transforms are designed by using different rotation angles at the final stage of the discrete cosine transforms (DCTs) butterfly flow-graph structure. More recently, it is found that a set of more efficient alternative transforms can be derived by introducing sign-flips at the same stage, which is equivalent to an extra rotation angle of π. In this paper, we generalize this sign-flipping technique by randomly embedding sign-flips into all stages of the DCTs butterfly structure so that the encryption space becomes much larger to yield a higher security. We pursue this study for H.264-compatible videos, assuming that the integer DCT of size 4 × 4 is used. First, we follow the separable implementation of the 4 × 4 2-D DCT in which different sign-flipping strategies will be employed along its horizontal and vertical dimensions. Second, we convert the 4 × 4 2-D DCT into a 16-point 1-D butterfly structure so that more sign-flips can be embedded at its various stages. Third, we choose different schemes to pair the node-variables in the 16-point 1-D butterfly structure, thus further enlarging the encryption space. Extensive experiments are conducted to show the performance of these improved encryption schemes and some security analyzes are also presented to confirm their persistence to various attacking strategies.

Toolgraph Design of Optimal and Feasible Control Strategies for Time‐Varying Dynamical Systems

The paper presents a new method for designing optimal and feasible control strategies for time‐variant dynamical processes. The key point of the presented idea lies in utilizing a flow graph structure for representing pertinent properties of the autonomous dynamics of a given dynamical process in a time‐and‐state space, which is composed of certain elementary segments. The structure is referred to as a time‐and‐state space toolgraph. In the procedure, each segment of the temporary state space is assigned a node of the time‐and‐state space toolgraph. The flow values are proportional to the cost of driving the operational point of the dynamical process between the centers of adjacent segments. Any of the discrete optimization algorithms can be applied to search for a cheapest path connecting the initial and terminal points of the sought optimal piecewise‐linear trajectory of the operational points in the considered time‐and‐state space. Additional assumptions or restrictions concerning arbitrary forbidden zones for the operational points can be easily taken into account. In such cases the nodes representing the segments partially or entirely belonging to the finite forbidden zones are deposed from the toolgraph structure.

Design of New Unitary Transforms for Perceptual Video Encryption

In our earlier work , we proposed for the first time that the perceptual video encryption be performed at the transformation stage by selecting one out of multiple unitary transforms according to the encryption key. In this letter, we aim to design some more efficient transforms to be used in this framework. Two criteria are followed for designing such transforms: 1) they are significantly different from discrete cosine transform (DCT) or discrete sine transform (DST), and 2) the resulted coding efficiency is exactly the same to what can be achieved by using DCT or just falls very slightly. As a result, we find that these transforms are actually derived by the sign-flipping on some node-variables in the flow-graph structure of DCT - a special case of the plane-based rotations (by π or 180°). Extensive simulations based on the H.264 codec are performed to demonstrate their effectiveness through both objective and subjective assessments. Finally, we present the security analysis to show the resistance of our algorithms to different types of attacks.

DESIGNING NONLINEAR CONTROL SYSTEMS BY STATE-SPACE FLOW GRAPH OPTIMIZATION

This paper presents a method for planning optimal control for nonlinear processes by using discrete optimization algorithms. The principal concept is to analyze the autonomous dynamics and to use its properties in the design of an optimal state-space trajectory. The analysis is performed in a multi-stage procedure, based on a proper decomposition of an operational subspace into a set of segments. The arrangement of these segments is transformed into a flow graph structure. Flow values characterize the cost of driving the operational point between two adjacent nodes. A discrete optimization algorithm is used to search the state-space graph for an optimal path.

A Pipeline Scheduling Algorithm for High-Level Synthesis

Scheduling is the most important task in high-level synthesis process, while pipelining is highly important for realising high-performance digital components. This paper presents a pipeline list-based scheduling algorithm, which performs forward and backward pipelining. The forward priority function is based on incorporating some information extracted from data flow graph (DFG) structure to guide the scheduler to find near-optimal/optimal schedules quickly. The algorithm has a flexible procedure cycle, which allow designers to make efficient area-performance trade-offs by using different strategies employed. Designers can choose between doing forward / backward pipelining with or without resource sharing combined with clock cycle selection, pipe stage delay determination. Experimental results with standard benchmarks show the effectiveness of the proposed algorithm.

A unified approach for scheduling and allocation

This paper presents a methodology for the integration of scheduling and allocation in high-level synthesis. It shows how a previous global analysis of the data flow graph structure and the module library features can be used as an appropriate guide to accelerate the process of finding solutions in the design space. Several bounding and guiding heuristics for a branch-and-bound-based exploration are presented. In addition to dealing with basic blocks, the scheduling and allocation method addresses also the treatment of conditional branches and loops.

A novel SFG structure for C-T high-pass filters

A signal flow graph (SFG) structure for simulating passive high-pass ladder filters, called the incremental integration structure, is proposed. The structure requires the use of integrators with nonintegrating inputs, and an implementation based on the MOSFET-C technique is discussed. The incremental integration structure is compared to the leapfrog and direct SFG simulation structures. Leapfrog high-pass filters are relatively simple and show good noise properties, but they are based on differentiators and thus stability problems exist. The direct SFG simulation method is based on integrators and has good stability properties, but it leads to a relatively high circuit complexity and a high noise level. However, the incremental integration structure inherits the low-noise properties of the leapfrog structure and the good stability of the direct SFG simulation method. A sixth-order elliptic high-pass filter chip with a passband frequency of 3.0 kHz has been manufactured, and measurements support the validity of the approach.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>