Abstract
Scheduling is the most important task in high-level synthesis process, while pipelining is highly important for realising high-performance digital components. This paper presents a pipeline list-based scheduling algorithm, which performs forward and backward pipelining. The forward priority function is based on incorporating some information extracted from data flow graph (DFG) structure to guide the scheduler to find near-optimal/optimal schedules quickly. The algorithm has a flexible procedure cycle, which allow designers to make efficient area-performance trade-offs by using different strategies employed. Designers can choose between doing forward / backward pipelining with or without resource sharing combined with clock cycle selection, pipe stage delay determination. Experimental results with standard benchmarks show the effectiveness of the proposed algorithm.
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