Floorplan Generation Research Articles

Procedural floor plan generation from building sketches

We present a method for automated reconstruction of building interiors from hand-drawn building sketches. Image processing is used to extract the building's outline and openings. Then, a procedural generation algorithm creates a floor plan according to user requisites. The proposed method handles a wide variety of input image styles and building shapes, including non-convex polygons. Possible applications include architectural tools and digital content generation.

Building seismic response and visualization using 3D urban polygonal modeling

Abstract The widely accessible 3D urban polygonal model is adopted herein to solve the two major challenges in urban seismic simulation: (1) building data acquisition and (2) high-fidelity visualization. A building identification method and a floor plan generation method are proposed in this study. These methods facilitate the automatic generation of 3D-GIS data of buildings, using the widely available 3D urban polygonal model and 2D-GIS data, to achieve the integrated earthquake simulation (IES)-based urban seismic simulation. In addition, a high-fidelity urban earthquake disaster scenario is generated based on the 3D urban polygonal model, the seismic simulation results from IES, and the proposed remeshing and displacement interpolation techniques, which is significantly more realistic than the existing 2.5D visualization method. The outcome of this research will provide a technical reference for improving emergency preparedness and mitigating possible earthquake-induced losses for high seismic regions and cities.

Area-performance trade-off in floorplan generation of Application-Specific Network-on-Chip with soft cores

Application-Specific Network-on-Chip (ASNoC) synthesis has found increasing significance in developing System-on-Chip (SoC) solutions for applications. This paper integrates various issues in the ASNoC synthesis process - availability of soft cores (with area and aspect ratio regulations), floorplanning for the whole NoC and determining router locations. Apart from attaching primary routers to the cores, it also introduces necessary extra secondary routers, so that the inter-router link length can be kept within a specified upper bound. A Particle Swarm Optimization (PSO) based formulation has been made to solve this integrated problem with a trade-off between the overall chip-area and the network communication overhead. Experimentation has been carried out with a set of well-known benchmarks. Apart from static communication cost, throughput, latency and energy consumption of the approach have been computed. The approach compares favourably with some recent approaches reported in the literature.

Floorplan-aware analog IC sizing and optimization based on topological constraints

This paper presents a methodology for analog IC circuit-level sizing and optimization, which takes into account the layout geometrical properties, by introducing a simple and general description that permits the inclusion of the floorplan generation in the sizing optimization loop with negligible computational costs. The usage of a modified NSGA-II state-of-the-art multi-objective multi-constraint optimization kernel enables the efficient exploration of design tradeoffs, while the inclusion of corner cases and the usage of the industrial circuit simulators (HSPICE®, Eldo® or Spectre®) ensures the accuracy and reliability of the solutions. Several layout templates that enclose the constraints defined by the designer are used to generate multiple floorplan solutions for each sizing solution during the synthesis process, giving the optimizer pertinent and accurate geometric layout information, e.g., area, width, length, wasted area, etc. Additionally, a built-in technology independent module generator facilitates the instantiation of multiple versions of each device, further increasing the exploration of possible geometric combinations and consequently packing of the floorplan with a minimum of wasted area. The developed tool, AIDA-C, implements the proposed approach, and is validated for both classical and new analog circuit structures using the UMC 130nm design process.

Automated approach for design generation and thermal assessment of alternative floor plans

This paper presents a prototype tool for the space planning phase, which automatically generates alternative floor plans, according to the architect's preferences and desires, and assesses their thermal performance by coupling it with dynamic simulation. A case study of a single-family house was carried out, which comprehended two design sets. The first set correspond to a single-level house and the second set is a two level house served by one stair. Each set is made up of twelve alternative floor plans that were automatically generated, assessed, and ranked according to their thermal performance. The ranking function weights and factors variability is analyzed. The results demonstrate that two level design solutions have the best thermal performance and, within each set, the difference between the best and the worst thermal performance individual may reach 17% in the first set and 35% in the second set.

Floorplanning for Partially Reconfigurable FPGAs

Partial reconfiguration on heterogeneous field-programmable gate arrays with millions of gates yields better utilization of its different types of resources by swapping in and out the appropriate modules of one or more applications at any instant of time. Given a schedule of sub-task instances where each instance is specified as a netlist of active modules, reconfiguration overhead can be reduced by fixing the position and shapes of modules common across all instances. We propose a global floorplan generation method PartialHeteroFP to obtain same positions for the common modules across all instances such that the heterogeneous resource requirements of all modules in each instance are satisfied, and the total half-perimeter wirelength over all instances is minimal. Experimental results establish that the proposed PartialHeteroFP produces floorplans very fast, with 100% match of common modules and thereby minimizing the partial reconfiguration overhead.

Physical Design Methodology for Godson-2G Microprocessor

The Godson-2G microprocessor is a high performance SOC which integrates a four-issue 64-bit high performance CPU core (called GS464), a DDR2/3 controller, a HyperTransport controller, a PCI/PCI-X controller, etc. It is physically implemented in 65 nm CMOS process and reaches the frequency of 1GHz with power consumption less than 4 W. The main challenges of Godson-2G physical implementation include nanometer process technology effects, high performance design targets, and tight schedule. This paper describes the key innovative features of physical design methodology which had been used in Godson-2G physical implementation, with particular emphasis on interconnect driven floorplan generation (ICD-FP), adapted boundary constraints design optimization (ABC-OPT), automatic register group clock tree generation methodology (ARG-CTS).

Automatic Real-Time Generation of Floor Plans Based on Squarified Treemaps Algorithm

A novel approach to generate house floor plans with semantic information is presented. The basis of this model is the squarified treemaps algorithm. Previously, this algorithm has been used to create graphical representations based on hierarchical information, such as, directory structures and organization structures. Adapted to floor plans generation, this model allows the creation of internal house structures with information about their features and functionalities. The main contributions are related to the robustness, flexibility, and simplicity of the proposed approach to create floor plans in real-time. Results show that different and realistic floor plans can be created by adjusting a few parameters.

Slicible rectangular graphs and their optimal floorplans

Rectangular dualization method of floorplanning usually involves topology generation followed by sizing. Slicible topologies are often preferred for their simplicity and efficiency. While slicible topologies can be obtained efficiently, existing linear-time algorithms for topology generation from a given rectangular graph does not guarantee slicible topologies even if one exists. Moreover, the class of rectangular graphs, known as inherently nonslicible graphs, do not have any slicible topologies. In this article, new tighter sufficiency conditions for slicibility of rectangular graphs are postulated and utilized in the generation of area-optimal floorplans. These graph-theoretic conditions not only capture a larger class of slicible rectangular graphs but also help in reducing the total effort for topology generation, and in solving problems of larger size.

A unified approach to topology generation and optimal sizing of floorplans

Existing algorithms for floorplan topology generation by rectangular dualization usually do not consider sizing issues. In this paper, given a rectangularly dualizable adjacency graph and a set of aspect ratios of the modules, a topology which is likely to yield an optimally sized floorplan, is produced first in a top-down fashion by an AI-based search technique with novel heuristic estimates based on size parameters. It is shown that for any rectangular graph, there exists a feasible topology using only either straight or Z-cutlines recursively within a bounding rectangle. The significance of this result is four-fold: (1) considerable acceleration of the heuristic search, (2) topology generation with minimal number of nonslice cores, (3) guaranteed safe routing order without addition of pseudo modules, and (4) design of an efficient bottom-up heuristic for optimal sizing. Experimental results show that this integrated method elegantly solves floorplan optimization problem for general including inherently nonslicible adjacency graphs.

CELLULAR ARRANGEMENT PROBLEMS WITH RANDOM FLOWS

Abstract In VLSI design, manufacturing systems, architectural floorplan generation, urban and suburban neighborhood configurations, the problem of integrating the layout of cell nodes and rouling links is extremely complex. In this paper, configuration of the topology of a set of cells in the plane where random ( lows occur between the cells is analyzed. The problem is formulated as a Quadratic Set Packing Problem on a graph and a branch and bound algorithm together with supporting computational experience is presented.

Knowledge‐Based Approach to Overall Configuration of Multistory Office Buildings

A knowledge‐based system (KBS) is described that generates space layout alternatives for multistory office buildings taking into account flexibility and functionality, as well as constraints imposed by the owner and codes. A methodology for the generation of rectangular floor plans at different levels of detail is also presented. The layout alternatives generated include information regarding the number of stories, dimensions of a typical floor, and the size and location of the service core, with space allocated for different components such as elevators, mechanical risers, and the service area. Multidisciplinary design criteria, such as flexibility of rental areas, compatibility with structural system, general energy efficiency, etc., are extracted from a variety of sources in the literature and considered in the generation and evaluation of layouts. This KBS module for space layout is part of an integrated design system for multistory buildings to assist at the preliminary design stage.

FIRGEN: a computer-aided design system for high performance FIR filter integrated circuits

The authors describe automatic architecture and floorplan generation techniques for integrated circuit fixed-coefficient FIR (finite impulse response) filters that can achieve high sample rates with compact layouts. These techniques have been implemented in a filter design system called FIRGEN that can automate the entire design from filter specifications to final chip layout. It can be retargeted to new cell libraries and place and route tools. Result on four chips designed with FIRGEN are presented. These achieve sample rates ranging from 25 MHz to 112 MHz. >

The generation of floor plans with circulation spaces

Floor plans with interior courtyards, circulation spaces, and prespecified number of exterior rooms, are generated. The approach is graph theoretic, that is, underlying graphs are generated and, then, based on those graphs, the floor plans are constructed.