Floating-point Research Articles

Plasma potential measurements using an emissive probe made of oxide cathode

A novel emissive probe consisting of an oxide cathode coating is developed to achieve a low operating temperature and long service life. The properties of the novel emissive probe are investigated in detail, in comparison with a traditional tungsten emissive probe, including the operating temperature, the electron emission capability and the plasma potential measurement. Studies of the operating temperature and electron emission capability show that the tungsten emissive probe usually works at a temperature of 1800 K–2200 K while the oxide cathode emissive probe can function at about 1200 K–1400 K. In addition, plasma potential measurements using the oxide cathode emissive probe with different techniques have been accomplished in microwave electron cyclotron resonance plasmas with different discharge powers. It is found that a reliable plasma potential can be obtained using the improved inflection point method and the hot probe with zero emission limit method, while the floating point method is invalid for the oxide cathode emissive probe.

IEEE-754 Precision- p base-β Arithmetic Implemented in Binary

We show how an IEEE-754 conformant precision- p base-β arithmetic can be implemented based on some binary floating-point and/or integer arithmetic. This includes the four basic operations and square root subject to the five IEEE-754 rounding modes, namely the nearest roundings with roundTiesToEven and roundTiesToAway, the directed roundings downwards and upwards, as well as rounding towards zero. Exceptional values like ∞ of NaN are covered according to the IEEE-754 arithmetic standard. The results of the precision- p base-β operations are computed using some underlying precision- q binary arithmetic. We distinguish two cases. When using a precision- q binary integer arithmetic, the base-β precision p is limited for all operations by β 2 p ≤ 2 q , whereas using a precision- q binary floating-point arithmetic imposes stronger limits on the base-β precision, namely β 2 p ≤ 2 q for addition and multiplication, β 2 p ≤ 2 q-1 for division and β 2 p ≤ 2 q -3 for the square root. Those limitations cannot be improved. The algorithms are implemented in a Matlab/Octave flbeta-toolbox with the choice of using uint64 or binary64 as underlying arithmetic. The former allows larger precisions, the latter is advantageous for the square root, whereas computing times are similar. The flbeta-toolbox offers precision- p base-β scalar, vector and matrix operations including sparse matrices as well as corresponding interval operations. The base β can be chosen in the range β ∊ [2,64]. The flbeta-toolbox will be part of Version 13 of INTLAB [ 18 ], the Matlab/Octave toolbox for reliable computing.

Analysis of the Practical Path of Vocational Education Serving Rural Revitalization by Digital Means and Philosophy of Technology

Abstract In this paper, based on digital means and technical philosophy, the histogram algorithm in the Light GBM model is used to calculate the floating point values of the raw data for the analysis of vocational education service for rural revitalization so that each of its features is converted into a histogram. In order to prevent the feature training overfitting problem of the Light GBM model, the LightGBM model is optimized by the iterative tree MPA algorithm, and the prediction model of returning to poverty risk based on IMPA-LightGBM is constructed. Starting from the current situation of vocational education service for rural revitalization, we put forward research hypotheses to realize the research design of vocational education accurate poverty alleviation service for rural revitalization and carry out an example analysis of vocational education service for rural revitalization combined with digital technology. The results show that in terms of model performance, the WAPE values of the return-to-poor risk values obtained from the prediction of the IMPA-LightGBM model are all lower than 5.5%, so the prediction effect is relatively satisfactory, and the return-to-poor risk values of poverty-eradicating households can be effectively predicted. On the practice road analysis, the standard deviation (SD) of the rural revitalization development index in China as a whole decreased from 0.63 to 0.52, which means that the differences in rural revitalization among provinces are decreasing. This study explores the synergistic development of the community of interest between vocational education and rural revitalization through the cultivation of new vocational farmers.

Fast and Clean: Auditable high-performance assembly via constraint solving

Handwritten assembly is a widely used tool in the development of highperformance cryptography: By providing full control over instruction selection, instruction scheduling, and register allocation, highest performance can be unlocked. On the flip side, developing handwritten assembly is not only time-consuming, but the artifacts produced also tend to be difficult to review and maintain – threatening their suitability for use in practice.In this work, we present SLOTHY (Super (Lazy) Optimization of Tricky Handwritten assemblY), a framework for the automated superoptimization of assembly with respect to instruction scheduling, register allocation, and loop optimization (software pipelining): With SLOTHY, the developer controls and focuses on algorithm and instruction selection, providing a readable “base” implementation in assembly, while SLOTHY automatically finds optimal and traceable instruction scheduling and register allocation strategies with respect to a model of the target (micro)architecture.We demonstrate the flexibility of SLOTHY by instantiating it with models of the Cortex-M55, Cortex-M85, Cortex-A55 and Cortex-A72microarchitectures, implementing the Armv8.1-M+Helium and AArch64+Neon architectures. We use the resulting tools to optimize three workloads: First, for Cortex-M55 and Cortex-M85, a radix-4 complex Fast Fourier Transform (FFT) in fixed-point and floating-point arithmetic, fundamental in Digital Signal Processing. Second, on Cortex-M55, Cortex-M85, Cortex-A55 and Cortex-A72, the instances of the Number Theoretic Transform (NTT) underlying CRYSTALS-Kyber and CRYSTALS-Dilithium, two recently announced winners of the NIST Post-Quantum Cryptography standardization project. Third, for Cortex-A55, the scalar multiplication for the elliptic curve key exchange X25519. The SLOTHY-optimized code matches or beats the performance of prior art in all cases, while maintaining compactness and readability.

Identifiable, But Not Visible: A Privacy-Preserving Person Reidentification Scheme

Person re-identification (Person Re-ID) is widely regarded as a promising technique to identify a target person through surveillance cameras in the wild. Nevertheless, person Re-ID leads to severe personal image privacy concerns as personal images are stipulated by laws and guidelines as private data. To address these concerns, this article explores the first solution for building a privacy-preserving person Re-ID system. Specifically, this article formulizes privacy-preserving person Re-ID as similarity metrics of encrypted feature vectors because the underlying operation of person Re-ID is to compute the similarity of feature vectors that are extracted from person images by a machine learning model. However, feature vectors are generally denoted by floating-point numbers. To this end, this article exploits a series of new encoding mechanisms and secure batch computing protocols to encrypt floating-point feature vectors and achieve the underlying operation of person Re-ID. Rigorous theoretical analyses demonstrate that this work achieves person Re-ID without compromising any personal image privacy. Furthermore, the proposed secure batch protocols significantly enhance the performance of privacy-preserving person Re-ID while outputting the same precision as the previous method.

FPGA Implementation of Metaheuristic Optimization Algorithm

Metaheuristic algorithms are gaining popularity amongst researchers due to their ability to solve nonlinear optimization problems as well as the ability to be adapted to solve a variety of problems. There is a surge of novel metaheuristics proposed recently, however it is uncertain whether they are suitable for FPGA implementation. In addition, there exists a variety of design methodologies to implement metaheuristics upon FPGA which may improve the performance of the implementation. The project begins by researching and identifying metaheuristics which are suitable for FPGA implementation. The selected metaheuristic was the Simulated Kalman Filter (SKF) which proposed an algorithm that was low in complexity and used a small number of steps. Then the Discrete SKF was adapted from the original metaheuristic by rounding all floating-point values to integers as well as setting a fixed Kalman gain of 0.5. The Discrete SKF was then modeled using behavioral modeling to produce the Binary SKF which was then implemented onto FPGA. The design was made modular by producing separate modules that managed different parts of the metaheuristic and Parallel-In-Parallel-Out configuration of ports was also implemented. The Discrete SKF was then simulated on MATLAB meanwhile the Binary SKF was implemented onto FPGA and their performance were measured based on chip utilization, processing speed, and accuracy of results. The Binary SKF produced speed increment of up to 69 times faster than the Discrete SKF simulation.

Software Support for Arbitrary Precision Arithmetic in Programming Languages

Arbitrary precision arithmetic, also known as bignum arithmetic, is a computational technique that allows programmers to perform arithmetic operations on numbers with significantly higher precision and magnitude than what is typically supported by the built-in numerical data types in programming languages. This technique is especially useful when working with extremely large or extremely precise numbers, such as in cryptography or scientific computations. Arbitrary precision arithmetic has many applications in the areas of Cryptography, Numerical Computation, Statistical Analysis, and High Precision measurements. For example, the calculation of the modulus in the RSA algorithm involves numbers with 1024-bit numbers and higher. An arithmetic calculation involving Multiplication and exponentiation of such numbers using Modulo arithmetic cannot be easily carried out in the existing programming Languages unless special software is provided. We can calculate the mathematical constant Pi to many thousand decimal places using the support provided in Programming Languages. Many programming languages provide built-in support for libraries for arbitrary precision arithmetic. We discuss the support provided in C/C++, Java and Python Languages with examples. Besides Programming Languages, Toolkits like Matlab and Sagemath also are used for scientific computation and special software support provided in these toolkits can enable arbitrary precision arithmetic. Most Programming Languages have support for floating-point arithmetic. We also discuss how arbitrary precision floating point arithmetic. can be supported in C/C++, Java, and Python. In addition, we discuss support for arbitrary precision integer arithmetic in Ruby, Javascript and Matlab and support for arbitrary precision floating point arithmetic in the Perl Language. Finally, we provide an example of computing the constant Pi to many decimal places using the sagemath tool.

Computation of parabolic cylinder functions having complex argument

Numerical methods for the computation of the parabolic cylinder function U(a,z) for real a and complex z are presented. The main tools are recent asymptotic expansions involving exponential and Airy functions, with slowly varying analytic coefficient functions involving simple coefficients, and stable integral representations; these two main methods can be complemented with Maclaurin series and a Poincaré asymptotic expansion. We provide numerical evidence showing that the combination of these methods is enough for computing the function with 5×10−13 relative accuracy in double precision floating point arithmetic.

Numerical Approximations of the Riemann–Liouville and Riesz Fractional Integrals

In this paper, the numerical algorithms for calculating the values of the left- and right-sided Riemann–Liouville fractional integrals and the Riesz fractional integral using spline interpolation techniques are derived. The linear, quadratic and three variants of cubic splines are taken into account. The estimation of errors using analytical methods are derived. We show four examples of numerical evaluation of the mentioned fractional integrals and determine the experimental rate of convergence for each derived algorithm. The high-precision calculations are executed using the 128-bit floating-point numbers and arithmetic routines.

Attention Round for post-training quantization

Quantization methods for convolutional neural network models can be broadly categorized into post-training quantization (PTQ) and quantization aware training (QAT). While PTQ offers the advantage of requiring only a small portion of the data for quantization, the resulting quantized model may not be as effective as QAT. To address this limitation, this paper proposes a novel quantization function named Attention Round. Unlike traditional quantization function that map 32 bit floating-point value w to nearby quantization levels, Attention Round allows w to be mapped to all possible quantization levels in the entire quantization space, expanding the quantization optimization space. The possibilities of mapping w to different quantization levels are inversely correlated with the distance between w and the quantization levels, regulated by a Gaussian decay function. Furthermore, to tackle the challenge of mixed precision quantization, this paper introduces a lossy coding length measure to assign quantization precision to different layers of the model, eliminating the need for solving a combinatorial optimization problem. Experimental evaluations on various models demonstrate the effectiveness of the proposed method. Notably, for ResNet18 and MobileNetV2, the PTQ approach achieves comparable quantization performance to QAT while utilizing only 1024 training data and 10 min for the quantization process.

SG-Float: Achieving Memory Access and Computing Power Reduction Using Self-Gating Float in CNNs

Convolutional neural networks (CNNs) are essential for advancing the field of artificial intelligence. However, since these networks are highly demanding in terms of memory and computation, implementing CNNs can be challenging. To make CNNs more accessible to energy-constrained devices, researchers are exploring new algorithmic techniques and hardware designs that can reduce memory and computation requirements. In this work, we present self-gating float (SG-Float), algorithm hardware co-design of a novel binary number format, which can significantly reduce memory access and computing power requirements in CNNs. SG-Float is a self-gating format that uses the exponent to self-gate the mantissa to zero, exploiting the characteristic of floating-point that the exponent determines the magnitude of a floating-point value and the error tolerance property of CNNs. SG-Float represents relatively small values using only the exponent, which increases the proportion of ineffective mantissas, corresponding to reducing mantissa multiplications of floating-point numbers. To minimize the accuracy loss caused by the approximation error introduced by SG-Float, we propose a fine-tuning process to determine the exponent thresholds of SG-Float and reclaim the accuracy loss. We also develop a hardware optimization technique, called the SG-Float buffering strategy, to best match SG-Float with CNN accelerators and further reduce memory access. We apply the SG-Float buffering strategy to vector-vector multiplication processing elements (PEs), which NVDLA adopts, in TSMC 40nm technology. Our evaluation results demonstrate that SG-Float can achieve up to 35% reduction in memory access power and up to 54% reduction in computing power compared with AdaptivFloat, a state-of-the-art format, with negligible power and area overhead. Additionally, we show that SG-Float can be combined with neural network pruning methods to further reduce memory access and mantissa multiplications in pruned CNN models. Overall, our work shows that SG-Float is a promising solution to the problem of CNN memory access and computing power.

An 8.8 TFLOPS/W Floating-Point RRAM-Based Compute-in-Memory Macro Using Low Latency Triangle-Style Mantissa Multiplication

High-precision computation with low latency and high energy efficiency is required for AI-driven application and scientific computing. Emerging compute-in-memory (CIM) technology shows a great potential to accelerate multiplication and accumulation (MAC) operations which are frequently executed in such scenarios. Resistive RAM (RRAM) is highly suitable for CIM due to its excellent features such as nonvolatility, small cell size and MAC-friendly structure. However, the existing RRAM CIMs focus on the acceleration of fixed-point/integer operations. Several works adopt the logic-CIM structure to support high-precision Floating-point (FP) calculations, but they require lots of cycles and area to perform a FP operation. To meet the need of low latency and high energy efficiency of widely used FP calculation, we propose an accelerated FP-MAC architecture, based on 40nm RRAM CIM array. A full-parallel data input scheme and triangle weights arrangement is proposed for low latency multi-bits multiplication. A non-uniformly grouped sense amplifiers (NUGSAs) array is adopted for energy and area saving. Experiments show that the proposed FP-MAC design achieves an energy efficiency of up to 8.8 TFLOPS/W at FP8 mode and 3.3 TFLOPS/W at bFP16 mode, and the computing latency is 3.34ns.

Stable approximation of Helmholtz solutions in the disk by evanescent plane waves

Superpositions of plane waves are known to approximate well the solutions of the Helmholtz equation. Their use in discretizations is typical of Trefftz methods for Helmholtz problems, aiming to achieve high accuracy with a small number of degrees of freedom. However, Trefftz methods lead to ill-conditioned linear systems, and it is often impossible to obtain the desired accuracy in floating-point arithmetic. In this paper we show that a judicious choice of plane waves can ensure high-accuracy solutions in a numerically stable way, in spite of having to solve such ill-conditioned systems. Numerical accuracy of plane wave methods is linked not only to the approximation space, but also to the size of the coefficients in the plane wave expansion. We show that the use of plane waves can lead to exponentially large coefficients, regardless of the orientations and the number of plane waves, and this causes numerical instability. We prove that all Helmholtz fields are continuous superposition of evanescent plane waves, i.e., plane waves with complex propagation vectors associated with exponential decay, and show that this leads to bounded representations. We provide a constructive scheme to select a set of real and complex-valued propagation vectors numerically. This results in an explicit selection of plane waves and an associated Trefftz method that achieves accuracy and stability. The theoretical analysis is provided for a two-dimensional domain with circular shape. However, the principles are general and we conclude the paper with a numerical experiment demonstrating practical applicability also for polygonal domains.

ApproxTrain: Fast Simulation of Approximate Multipliers for DNN Training and Inference

Edge training of Deep Neural Networks (DNNs) is a desirable goal for continuous learning; however, it is hindered by the enormous computational power required by training. Hardware approximate multipliers have shown their effectiveness in gaining resource-efficiency in DNN inference accelerators; however, training with approximate multipliers is largely unexplored. To build resource-efficient accelerators with approximate multipliers supporting DNN training, a thorough evaluation of training convergence and accuracy for different DNN architectures and different approximate multipliers is needed. This paper presents ApproxTrain1, an open-source framework that allows fast evaluation of DNN training and inference using simulated approximate multipliers. ApproxTrain is as user-friendly as TensorFlow (TF) and requires only a high-level description of a DNN architecture along with C/C++ functional models of the approximate multiplier. We improve the speed of the simulation at the multiplier level by using a novel LUT-based approximate floating-point (FP) multiplier simulator on GPU (AMSim). Additionally, a novel flow is presented to seamlessly convert C/C++ functional models of approximate FP multipliers into AMSim. ApproxTrain leverages CUDA and efficiently integrates AMSim into the TensorFlow library to overcome the absence of native hardware approximate multiplier in commercial GPUs. We use ApproxTrain to evaluate the convergence and accuracy performance of DNN training with approximate multipliers for three application domains: image classification, object detection, and neural machine translation. The evaluations demonstrate similar convergence behavior and negligible change in test accuracy compared to FP32 and Bfloat16 multipliers. Compared to CPU-based approximate multiplier simulations in training and inference, the GPU-accelerated ApproxTrain is more than 2500× faster. Based on highly optimized closed-source cuDNN/cuBLAS libraries with native hardware multipliers, the original TensorFlow is, on average, only 8× faster than ApproxTrain.

Optimizing FPGA-Based DNN Accelerator With Shared Exponential Floating-Point Format

Optimizing FPGA-Based DNN Accelerator With Shared Exponential Floating-Point Format

MDCIM: MRAM-Based Digital Computing-in-Memory Macro for Floating-Point Computation with High Energy Efficiency and Low Area Overhead

Computing-in-Memory (CIM) is a novel computing architecture that enormously improves energy efficiency and reduces computing latency by avoiding frequent data movement between the computation and memory units. Currently, digital CIM is regarded as more suitable for high-precision operations represented in floating-point arithmetic, as it is not limited by the bit width of ADC/DAC in analog CIM. However, the development of DCIM still faces two problems: On the one hand, mainstream SRAM-based DCIM memory cells introduce large area overheads, which contain at least six transistors per cell. On the other hand, existing DCIM solutions can only support the computing precision up to FP32, failing to meet the demands of high-accuracy application scenarios. To overcome these problems, this work designs a novel SOT-MRAM-based digital CIM macro (MDCIM) with higher area/energy efficiency and achieves double-precision floating-point (FP64) computation with a modified fused multiply–accumulate (FMA) module. The proposed design is synthesized with a 55 nm CMOS technology node, achieving 0.62 mW power consumption, 26.9 GOPS/W, and 0.332 GOPS/mm2 energy efficiency at 150 MHz with 1.08 V supply. Circuit level simulation results show that the MDCIM can achieve higher area utilization compared to previous SRAM-based CIM designs.

Development of floating point operating devices

The paper shows a well-known approach to the construction of cores in multi-core microprocessors, which is based on the application of a data flow graph-driven calculation model. The architecture of such kernels is based on the application of the reduced instruction set level data flow model proposed by Yale Patt. The object of research is a model of calculations based on data flow management in a multi-core microprocessor. The results of the floating-point multiplier development that can be dynamically reconfigured to handle five different formats of floating-point operands and an approach to the construction of an operating device for addition-subtraction of a sequence of floating-point numbers are presented, for which the law of associativity is fulfilled without additional programming complications. On the basis of the developed circuit of the floating-point multiplier, it is possible to implement various variants of the high-speed multiplier with both fixed and floating points, which may find commercial application. By adding memory elements to each of the multiplier segments, it is possible to get options for building very fast pipeline multipliers. The multiplier scheme has a limitation: the exponent is not evaluated for denormalized operands, but the standard for floating-point arithmetic does not require that denormalized operands be handled. In such cases, the multiplier packs infinity as the result. The implementation of an inter-core operating device of a floating-point adder-subtractor can be considered as a new approach to the practical solution of dynamic planning tasks when performing addition-subtraction operations within the framework of a multi-core microprocessor. The limitations of its implementation are related to the large amount of hardware costs required for implementation. To assess this complexity, an assessment of the value of the bits of its main blocks for various formats of representing floating-point numbers, in accordance with the floating-point standard, was carried out.

A hybrid intelligent model based on logistic regression and fuzzy multiple-attribute decision-making for credit evaluation

. One of the crucial issues in data mining is to select an appropriate classification algorithm. Due to it usually involves many criteria, the duty of algorithm selection can be widely described as multiple-attribute decision-making (MADM) problems, including credit risk evaluation. Many different MADM approaches select classifiers based on different perspectives, and hence they might generate diverse classifiers' rankings. This paper aims to propose a hybrid intelligent model to overcome credit risk assessment problems based on logistic regression and the fuzzy MADM method. Firstly, the Ordinal Priority Approach (OPA) method evaluates attributes involved in credit risk problems by considering professional assessments of a decision-maker and calculates a weight for each criterion. Secondly, all categorical data converted into triangular-fuzzy numbers (TFNs) and numerical data are evaluated using the MADM instrument to obtain an optimal solution dataset and logistic regression to calculate the probabilities of the optimal dataset. In this experimental study, three existing classification techniques and the proposed intelligent model evaluate three banking credit datasets with a different number of criteria under numerical and categorical data types. The prediction accuracy results generated by the proposed model are compared with the three existing classification methods. The results exhibit that there are slight differences between the three datasets. The experimental results demonstrate the proposed intelligent model has superiority in classifying the credit loan recipients especially for categorical datasets.

Towards Efficient Dynamic Binary Translation Optimizations Based on RISC Architectural Features

Dynamic binary translation (DBT) is a core technology that enables the migration of legacy software to different instruction set architectures while maintaining the original semantics. However, the development and maintenance of an efficient cross-DBT system are challenging. Key challenges include memory access overhead, inefficient instruction simulation, and frequent context switches. In this paper, we propose three novel optimization techniques. First, we formalize a register mapping cost model and investigate a hierarchical register mapping approach to bridge the memory access overhead. Second, we accelerate floating point (FP) emulation by surrounding the use of hardware FP unit with high-efficiency non-FP code. Third, we present a function inlining approach to alleviating the overhead associated with indirect control lookup. On the system side, we implement our approach on ARM64 and SW64 architectures based on QEMU and extensively evaluate the effectiveness with the SPEC2006 benchmark suite. The experimental results show that an average of 1.28× performance speedup and 13.41% code size reduction can be achieved on SW64. Similarly, on ARM64, we achieve an average of 1.15× performance speedup and 11.48% code size reduction.

LUT‐DSP usage trade‐off for re‐configurable convolution acceleration core based on small logarithmic floating point representation

AbstractThe challenge in designing the high‐performance field‐programmable gate array (FPGA)‐based convolution accelerator is to take full advantage of the on‐chip computing resources. The reported CNN accelerators always exhaust the on‐chip DSPs and leave other computing resources under‐utilized. Hence, this brief presents a novel convolution acceleration core based on the small logarithmic floating‐point (SLFP) format, which results in three contributions. (1) The SLFP<3,5> multiplier is only implemented with LUT6s and operates at 650 MHz with the aid of the carry chain, which provides sufficient accuracy for most CNNs. In addition, a similar structure can be used to implement a SLFP<3,5> divider. (2) The DSPs in the TWO24 SIMD mode are cascaded to implement a 9‐input adder tree. The sum of the multiples of elements (e.g., , ) is easily obtained by configuring the last DSP in the 9‐input adder tree in the accumulation mode, which can support more kernels (e.g., , ) with a high utilization rate ( ). (3) The convolution core based on the SLFP format only uses LUT6s and DSPs to achieve 1300 MOPS, 433 MOPS, and 81 MOPS for , , and kernel, respectively. In summary, the proposed convolution accelerator not only balances the resource usage of LUT6s and DSPs but also quantizes most CNN models using several simple scaling operations instead of a computing‐intensive retraining algorithm because the distribution of SLFP numbers is very similar to FP32 numbers.