Floating-point Register Files Research Articles

Design and Assertion Based Verification of RISC-V Processor Subsystems

RISC-V is an open, free standard architecture. As its open-source architecture, it can be used in multiple applications like embedded processors, IoT, artificial intelligence, machine learning, military and defense applications. The parameters like throughput, performance, high speed etc., become essential in designing processor architecture. Pipelining is one such unique feature supported by RISC-V ISA, which basically involves the execution of multiple instructions in single cycle. This feature helps in improving the performance of the processor architecture. RISC-V ISA supports five stages of pipelining they are instruction fetch, instruction decode, execute, memory and write-back stage. The work covered in this paper involves the design and implementation of the subsystems of the RISC-V ISA which are present in different stages of pipeline architecture. The subsystems included in this work are Floating Point Unit (FPU) of Execute stage, Branch Prediction Unit (BPU) of instruction fetch stage, Forwarding Unit of execution stage, Operand Logic of decode stage and Floating-Point register file of Write-back stage. These subsystems are designed using Verilog Hardware Description Language in Xilinx ISE. Followed by the implementation the verification of the floating-point unit and the forwarding unit is performed using System Verilog Assertions in QuestaSim. The Assertion coverage report for the same is extracted.

Multi‐level simultaneous multithreading scheduling to reduce the temperature of register files

SUMMARYSimultaneous multithreading (SMT) processors can exploit thread‐level parallelism and at the same time exploit instruction‐level parallelism for multiple‐issue, dynamically scheduled processors. As they have been widely used in embedded systems, reducing their highest temperature has become very important. According to our observation, the register file is always one of the hottest parts of an embedded system. Thus, we present a smart scheduling that can cool an SMT processor effectively by controlling the temperatures of its register files without causing significant performance loss. The proposed approach is fourfold, thus allowing an operating system to dynamically adjust the running workloads based on the temperature threshold and the real‐time constraint. Our experiment was performed on the M‐Sim and HotSpot simulators to evaluate the power of functional units and the temperature impact for SMT processors. In contrast with the round‐robin scheduling, the proposed approach can reduce thermal emergency time by 16.1 and 9.38% of the integer register file and the floating point register file, respectively. Moreover, the proposed approach only degrades performance by 8.8%, which is better than the 22.1% of the throttling approach. Copyright © 2011 John Wiley & Sons, Ltd.

Selective Writeback: Reducing Register File Pressure and Energy Consumption

Much of the complexity in today's superscalar microprocessors stems from the need to maintain the speculatively produced results within the on-chip storage components until these results can be safely discarded without endangering the reconstruction of the precise state or impeding the recovery from possible branch misspeculations. For this, modern designs use large, heavily-ported physical register files (RFs) to increase the instruction throughput. The high complexity and power dissipation of such RFs mainly stem from the need to maintain each and every result for a large number of cycles after the result generation. We observed that a significant fraction (about 45%) of the result values are delivered to their consumers via the bypass network (consumed ldquoon-the-flyrdquo) and are never read out from the destination registers. In this paper, we first formulate conditions for identifying such transient values and describe their microarchitectural implementation; then we propose a technique to avoid the writeback of such transient values into the RF. With 64-entry integer and floating point register files, our technique achieves an 11% performance improvement and 29% reduction in the RF energy consumption compared to the baseline machine with the same number of registers. Furthermore, for the same performance target, the selective writeback scheme results in a 38% reduction in the energy consumption of the RF compared to the baseline machine.

The Parity Protected, Multithreaded Register Files on the 90-nm Itanium Microprocessor

The integer and floating-point register files of the 90-nm generation Itanium Microprocessor are described. A pulsed, shared word line technique enables a 22 ported integer array with only 12 word lines per register. An in-register ripple parity system provides soft error detection with no impact to operand bypass or pipeline depth while keeping consuming less that 6% of the total register datapath area. The register file implements temporal multi-threading by multiplexing the read and write ports to two storage nodes enabling registers to write both foreground and background threads to the same register at the same time. Thread switching completes in one cycle. The register files are fabricated in a 7-layer 90-nm process and operate up to 2.0 GHz while consuming 400 mW per register array.

IBM PowerPC 440 FPU with complex-arithmetic extensions

The PowerPC® 440 floating-point unit (FPU) with complex-arithmetic extensions is an embedded application-specific integrated circuit (ASIC) core designed to be used with the IBM PowerPC 440 processor core on the Blue Gene®/L compute chip. The FPU core implements the floating-point instruction set from the PowerPC Architecture™ and the floating-point instruction extensions created to aid in matrix and complex-arithmetic operations. The FPU instruction extensions define double-precision operations that are primarily single-instruction multiple-data (SIMD) and require two (primary and secondary) arithmetic pipelines and floating-point register files. However, to aid complex-arithmetic routines, some FPU extensions actually perform different (yet closely related) operations while executing in the arithmetic pipelines. The FPU core implements an operand crossbar between the primary and secondary arithmetic datapaths to enable each pipeline operand access from the primary or secondary register file. The PowerPC 440 processor core provides 128-bit storage buses and simultaneous issue of an arithmetic instruction with a storage instruction, allowing the FPU core to fully utilize the parallel arithmetic pipes.

Developing the WTL3170/3171 Sparc floating-point coprocessors

The development of the first two members in a family of scalable-processor-architecture (Sparc)-compatible parts is described. With varying frequency and latency performance, the chips work with the first two integer unit (IU) implementations from other Sparc vendors. These are the first Sparc chips to integrate all floating-point controller functions, floating-point register files, and 64-b ALU (arithmetic and logic unit), multiplier, and divide/square-root units in one die. A strong relationship with original equipment manufacturers in system behavioral-level modeling and a short time to production were key factors in the product development plan. Implementation goals, bus organization, overall processor operation, and the operation of the ALU, multiplier, and divide/square-root units are discussed. >