Abstract
The development of the first two members in a family of scalable-processor-architecture (Sparc)-compatible parts is described. With varying frequency and latency performance, the chips work with the first two integer unit (IU) implementations from other Sparc vendors. These are the first Sparc chips to integrate all floating-point controller functions, floating-point register files, and 64-b ALU (arithmetic and logic unit), multiplier, and divide/square-root units in one die. A strong relationship with original equipment manufacturers in system behavioral-level modeling and a short time to production were key factors in the product development plan. Implementation goals, bus organization, overall processor operation, and the operation of the ALU, multiplier, and divide/square-root units are discussed. >
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