Floating-point Instruction Set Research Articles

Vectorization Programming Based on HR DSP Using SIMD

Single instruction multiple data (SIMD) vector extension has become an essential feature of high-performance processors. Architectures such as x86, ARM, MIPS, and PowerPC have specific vector extension instruction sets and SIMD micro-architectures. Using SIMD vectorization programming can significantly improve the performance of application algorithms while keeping the hardware overhead low. In addition, other methods can enhance algorithm performance, such as selecting the best SIMD vectorization model for algorithms, ensuring sufficient instruction streams, implementing reasonable and effective cache data prefetching, and aligning data access and storage addresses according to instruction characteristics. The goal of this paper is three-fold. First, we introduce the basic structural characteristics of a general RISC processor, Hua Rui (HR) DSP, with a custom vector instruction set based on compatibility with an MIPS64 fixed-point and floating-point instruction set, as well as a Fei Teng (FT) processor compatible with an ARMv8 instruction set. Second, we summarize the fundamental principles of SIMD vectorization programming design for the HR DSP, which provides ideas for other scholars or engineering and technical personnel to study the algorithm performance using SIMD vectorization optimization. Third, we implement representative typical algorithms based on the HR and FT platforms and obtain experimental results that show improvement in algorithm SIMD vectorization optimization according to the vector programming design principles summarized in this article can improve the single-core performance of scalar implementation without vectorization, instruction streams, and cache data prefetching by 4–22 times for mean filter, accumulation, and matrix–matrix multiplication, which is significantly better than the performance improvement of 3–13 times for the FT platform. Moreover, the performance of matrix–matrix multiplication using the best vectorization model on the HR platform is about 84% higher than that of the common SIMD vectorization model.

Design of RISC Processor with IEEE754 Standard Floating-Point Instruction Set in FPGA using VHDL for Digital Signal Processing Applications

The design of RISC processors, which are the key of digital signal processing applications, are increasing in reconfigurable hardware. FPGAs are suitable reconfigurable hardware for RISC processor design, with advantages such as parallel processing and low power consumption. In this study, the design of the 32-bit RISC processor in a FPGA is presented. The designed RISC processor contains IEEE754 standard floating-point number processing unit, which is executed in a one clock cycle. The verification of the processor is performed for the Zynq-7000 SoC Artix-7 FPGA chip in the Xilinx Vivado tool. Classification of an artificial neural network using the iris dataset is carried out in this designed RISC processor. In order to compare the performance, the same artificial neural network is executed in real time within the dual-core ARM Cortex-A9 processor in the operating system of the Zynq-7000 SoC. The results show that the RISC processor designed in the FPGA executes at 20x less clock cycles and 3x higher speed compared to the ARM processor.

Stochastic optimization of floating-point programs with tunable precision

The aggressive optimization of floating-point computations is an important problem in high-performance computing. Unfortunately, floating-point instruction sets have complicated semantics that often force compilers to preserve programs as written. We present a method that treats floating-point optimization as a stochastic search problem. We demonstrate the ability to generate reduced precision implementations of Intel's handwritten C numeric library which are up to 6 times faster than the original code, and achieve end-to-end speedups of over 30% on a direct numeric simulation and a ray tracer by optimizing kernels that can tolerate a loss of precision while still remaining correct. Because these optimizations are mostly not amenable to formal verification using the current state of the art, we present a stochastic search technique for characterizing maximum error. The technique comes with an asymptotic guarantee and provides strong evidence of correctness.

IBM PowerPC 440 FPU with complex-arithmetic extensions

The PowerPC® 440 floating-point unit (FPU) with complex-arithmetic extensions is an embedded application-specific integrated circuit (ASIC) core designed to be used with the IBM PowerPC 440 processor core on the Blue Gene®/L compute chip. The FPU core implements the floating-point instruction set from the PowerPC Architecture™ and the floating-point instruction extensions created to aid in matrix and complex-arithmetic operations. The FPU instruction extensions define double-precision operations that are primarily single-instruction multiple-data (SIMD) and require two (primary and secondary) arithmetic pipelines and floating-point register files. However, to aid complex-arithmetic routines, some FPU extensions actually perform different (yet closely related) operations while executing in the arithmetic pipelines. The FPU core implements an operand crossbar between the primary and secondary arithmetic datapaths to enable each pipeline operand access from the primary or secondary register file. The PowerPC 440 processor core provides 128-bit storage buses and simultaneous issue of an arithmetic instruction with a storage instruction, allowing the FPU core to fully utilize the parallel arithmetic pipes.

A floating-point to fixed-point assembly program translator for the TMS 320C25

A floating-point digital signal processor-like programming environment is developed for the Texas Instruments TMS 320C25, a fixed-point digital signal professor. Programmers first develop an assembly program using a hypothetical floating-point instruction set and a floating-point data format. Then, floating-point simulation of the assembly program is conducted not only for verifying the program but also for estimating the range of each internal variable. This program is then automatically translated into a fixed-point version. The scaling that is needed for the conversion of floating-point variables and data to fixed-point counterparts is conducted based on the range of the signal being processed. Since the floating-point program is executed after being converted to a fixed-point version, the execution speed is not sacrificed. In addition, the implementation result shows a higher SQNR than that employing conventional scaling approaches because scaling is conducted based on the statistics of a real signal. Therefore, this software provides the convenience of floating-point programming without sacrificing the advantages of fixed-point digital signal processors. Application examples for a fourth-order IIR filter, Levinson-Durbin's recursion, and an FFT routine are presented. >

Turbo-simulation: A technical note

Many reported computer execution-speed benchmarks involve artificial programs exploring the fixed- and floating-point instruc tion sets. Instead, we report results from two actual dynamic- system simulation problems long used as benchmarks by the simulation community. PHYSBE (Korn and Wait 1978) is a blood- circulation model used in physiological studies, and the Hidinger benchmark (Hidinger 1982) is a practical three-dimensional flight simulation (really a torpedo/ autopilot simulation) developed at the Naval Ocean Systems Center. Such programs can give realistic indications of practical results obtainable with different machines. Specifically, we report on a study of measured and predicted simulation speeds of personal computers with speeded-up clocks and of new 32-bit personal computers. This is a glimpse into a new, bright world of very cost-effective simulation; an 80386/ 387-based PC clone outruns a timeshared VAX 11/780 in the flight-simulation benchmark.

A monolithic 64 bit floating-point coprocessor

A double/single-precision floating-point processor using a titanium disilicide 3.5-/spl mu/m NMOS process achieves double-precision add/subtract, multiply, and divide in 2, 8, and 16 /spl mu/s respectively. The chip has about 35K devices and is about 400 mil on the side. The chip uses a single 5-V supply with TTL-compatible levels on all signals except for the clocks, which require 4.5 V for a logic high. Four input clocks are used to generate eight 50-ns intervals. A -2.5 V substrate bias generator is designed on the chip but uses a pin for an external capacitor. The processor, which is to be used in a desktop implementation of a minicomputer, executes the floating-point instruction set for the micro-Eclipse computer.

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