Floating-point Fast Fourier Transform Research Articles

Design of FFT processor using low power Vedic multiplier for wireless communication

Digital Signal Processing (DSP) is a very significant and active research area. High throughput is a requirement for most wireless communication systems. The critical bottleneck that affects communication ability is the Fast Fourier Transform (FFT), which is the essence of most modulators. Currently, Floating point FFT processors have been used in Radar signal processing, fast convolution, Spectrum estimation and OFDM based modulators/demodulators. Efficient VLSI based architectures are required for real-time FFT processing. The multiplication limits the performance in terms of throughput of FFT. Consequently, there is a need for high speed and low power multiplier architectures with minor truncation error. The present paper presents a modified binary floating-point multiplier using Vedic mathematics and a modification in the previously published Vedic multiplier circuit has been proposed. The entire design has been implemented in Verilog HDL. Synthesis and simulations are done using Xilinx ISE Design Suite 14.5.The performance evaluation in terms of speed and area occupied is compared with the previously reported Vedic multiplier architectures. Using 90 nm technologies, the Power Delay Product (PDF) of the proposed Vedic multiplier gets reduced through KSA by 86.41% compared to the multipliers. The Vedic adder power is reduced by 45.9% when it is compared with the carry look-ahead adder. The overall power delay product is reduced around 55–60% through the FFT processor by using Vedic mathematics.

Double Precision Floating Point Fft Processor using Vedic Mathematics

There should be rapid, efficient and simple process for every scenario now a day. To compute the N point DFT, Fast Fourier Transform (FFT) is a productive algorithm. It has great applications in communication, signal and image processing and instrumentation. In the implementation of FFT one of the challenges is the complex multiplications, so to make this process rapid and simple it’s necessary for a multiplier to be fast and power efficient. To tackle this problem Karatsuba sutra and Nikhilam sutra are an efficient method of multiplication in Vedic Mathematics. This paper will present a design methodology of Double Precision Floating Point Fast Fourier Transform (FFT) Processor.The execution time and complexity can be reduced by the algorithm which is there in Vedic.The main aim is to make FFT Processor process rapid and simple by designing a multiplier which is fast and power efficient by using double precision floating point and Vedic Mathematics concepts.

Low-Power Floating-Point Adaptive-CORDIC-Based FFT Twiddle Factor on 65-nm Silicon-on-Thin-BOX (SOTB) With Back-Gate Bias

In this brief, a silicon-on-thin-BOX (SOTB) implementation of single-precision floating-point fast-Fourier-transform (FFT) twiddle factor (TF) is presented. The architecture of the proposed TF is developed based on the adaptive method of the coordinate rotation digital computer (CORDIC) algorithm. The 65-nm SOTB technology was chosen because of its ultra-low-power advantage. Furthermore, the back-gate bias technique can be applied on an SOTB chip to adjust the operation for high-performance or low-power requirement. The layout of the SOTB 65-nm TF core is about 22869 gate-count on the die area of 86721 $ \mu \text {m}^{2}$ . The measurement results show that the core reached its highest operating frequency of 55 MHz at the 1.2-V supply voltage (VDD) with the forward back-gate bias (FBB) ≥ 1.5 V. The power and energy consumptions at this point were 1.54 mW and 27.91 pJ/cycle, respectively. The lowest operating VDD was at 0.5 V with the FBB ≥ 0.5 V. In the standby mode, when the clock-gating technique was deployed, the leakage current can be reduced to 0.4 nA at the 0.4 V VDD and −2.5-V reverse back-gate bias (RBB).

A reconfigurable 4-GS/s power-efficient floating-point FFT processor design and implementation based on single-sided binary-tree decomposition

This paper presents a high throughput size-configurable floating point (FP) Fast Fourier Transform (FFT) processor, having implemented the 8-parallel multi-path delay feedback (MDF) functions suitable for applications in the real-time radar imaging system. With regard to floating-point FFT design, to acquire a high throughput with restricted area and power consumptions poses as a greater challenge due to some higher degrees of complexity involved in realizing of FP operations than those fixed-point counterparts. To address the related issues, a novel mixed-radix FFT algorithm featuring the single-sided binary-tree decomposition strategy is proposed aiming at effectively containing the complexity of multiplications for any 2k-point FFT. To this aid, the parallel-processing twiddle factor generator and the dual addition-and-rounding fused FP arithmetic units are optimized to meet the high accuracy demand in computation and the low power budget in implementation. The proposed FP FFT processor has been designed in silicon based on SMIC's 28 nm CMOS technology with the active area of 1.39 mm2. The prototype design delivers a throughput of 4 GSample/s at 500 MHz, at a peak power consumption of 84.2 mW. Thus, the proposed design approach achieves a significant improvement in power efficiency approximately by 14 times on average over some other FP FFT processors previously reported.

An area- and energy-efficient hybrid architecture for floating-point FFT computations

Floating-point fast Fourier transform (FFT) has been widely expected in scientific computing and high-resolution imaging applications due to the wide dynamic range and high processing precision. However, it suffers high area and energy overhead problems in comparison to fixed-point implementations. To address these issues, this paper presents an area- and energy-efficient hybrid architecture for floating-point FFT computations. It minimizes the required arithmetic units and reduces the memory usage significantly by combining three different parts. The serial radix-4 butterfly (SR4BF) is used in the single-path delay commutator (SDC) part to minimize the required arithmetic units with 100% adder utilization ratio obtained. A modified single-path delay feedback (MSDF) architecture is proposed to achieve a tradeoff between arithmetic resources and memory usage by using the new half radix-4 butterfly (HR4BF) with 50% adder utilization ratio obtained. The intermediate caching buffer is modified accordingly in the MSDF part. By combining both the advantages on arithmetic units reducing and memory usage optimization in different parts, the optimized area and power are obtained without throughput loss. The logic synthesis results in a 65 nm CMOS technology show that the energy per FFT is about 331.5 nJ for 1024-point FFT computations at 400 MHz. The total hardware overhead is equivalent to 460k NAND2 gates.

Configurable Floating‐Point FFT Accelerator on FPGA Based Multiple‐Rotation CORDIC

Fast Fourier transform (FFT) accelerator and Coordinate rotation digital computer (CORDIC) algorithm play important roles in signal processing. We propose a configurable floating-point FFT accelerator based on CORDIC rotation, in which twiddle direction prediction is presented to reduce hardware cost and twiddle angles are generated in real time to save memory. To finish CORDIC rotation efficiently, a novel approach in which segmented-parallel iteration and compress iteration based on CSA are presented and redundant CORDIC is used to reduce the latency of each iteration. To prove the efficiency of our FFT accelerator, four FFT accelerators are prototyped into a FPGA chip to perform a batch-FFT. Experimental results show that our structure, which is composed of four butterfly units and finishes FFT with the size ranging from 64 to 8192 points, occupies 33230(3%) REGs and 143006(30%) LUTs. The clock frequency can reach 122MHz. The resources of double-precision FFT is only about 2.5 times of single-precision while the theoretical value is 4. What's more, only 13331 cycles are required to implement 8192-points double-precision FFT with four butterfly units in parallel.

Area efficient floating‐point FFT butterfly architectures based on multi‐operand adders

Hardware implementation of the fast Fourier transform (FFT) function consists of multiple consecutive arithmetic operations over complex numbers. Applying floating-point arithmetic to FFT coprocessors leads to a wider dynamic range and allows the coprocessor to collaborate with general purpose processors via the standard floating-point arithmetic. This offloads compute-intensive tasks from the primary processor and overcomes floating-point concerns such as scaling and overflow/underflow detection. The downside, however, is that floating-point units are slower than the fixed-point counterparts. One of the popular ways to improve the speed of floating-point FFT units is to merge the arithmetic operations inside the butterfly units of a FFT architecture. This leads to a butterfly architecture based on multi-operand adders. Butterfly units are designed, in two of the most recent works, using three-operand and four-operand adders. However, the work reported here by the present authors goes further and a butterfly architecture based on a five-operand adder is proposed. Simulation results demonstrate that the proposed butterfly architecture is 50% smaller than the fastest previous work with about 17% latency overhead. Compared with the smallest previous work, the proposed design is 47% smaller and 8% faster.

Low power reconfigurable FP-FFT core with an array of folded DA butterflies

A variable length (32 ~ 2,048), low power, floating point fast Fourier transform (FP-FFT) processor is designed and implemented using energy-efficient butterfly elements. The butterfly elements are implemented using distributed arithmetic (DA) algorithm that eliminates the power-consuming complex multipliers. The FFT computations are scheduled in a quasi-parallel mode with an array of 16 butterflies. The nodes of the data flow graph (DFG) of the FFT are folded to these 16 butterflies for any value of N by the control unit. Register minimization is also applied after folding to decrease the number of scratch pad registers to (log 2 N − 1) × 16. The real and imaginary parts of the samples are represented by 32-bit single-precision floating point notation to achieve high precision in the results. Thus, each sample is represented using 64 bits. Twiddle factor ROM size is reduced by 25% using the symmetry of the twiddle factors. Reconfigurability based on the sample size is achieved by the control unit. This distributed floating point arithmetic (DFPA)-based design of FFT processor implemented in 45-nm process occupies an area of 0.973 mm2 and dissipates a power of 68 mW at an operating frequency of 100 MHz. When compared with FFT processor designed in the same technology with multiplier-based butterflies, this design shows 33% less area and 38% less power. The throughput for 2,048-point FFT is 222 KS/s and the energy spent per FFT is 7.4 to 14 nJ for 64 to 2,048 points being one among the most energy-efficient FFT processors.

An FPGA-Based Embedded Robust Speech Recognition System Designed by Combining Empirical Mode Decomposition and a Genetic Algorithm

A field-programmable gate array (FPGA)-based robust speech measurement and recognition system is the focus of this paper, and the environmental noise problem is its main concern. To accelerate the recognition speed of the FPGA-based speech recognition system, the discrete hidden Markov model is used here to lessen the computation burden inherent in speech recognition. Furthermore, the empirical mode decomposition is used to decompose the measured speech signal contaminated by noise into several intrinsic mode functions (IMFs). The IMFs are then weighted and summed to reconstruct the original clean speech signal. Unlike previous research, in which IMFs were selected by trial and error for specific applications, the weights for each IMF are designed by the genetic algorithm to obtain an optimal solution. The experimental results in this paper reveal that this method achieves a better speech recognition rate for speech subject to various environmental noises. Moreover, this paper also explores the hardware realization of the designed speech measurement and recognition systems on an FPGA-based embedded system with the System-On-a-Chip (SOC) architecture. Since the central-processing-unit core adopted in the SOC has limited computation ability, this paper uses the integer fast Fourier transform (FFT) to replace the floating-point FFT to speed up the computation for capturing speech features through a mel-frequency cepstrum coefficient. The result is a significant reduction in the calculation time without influencing the speech recognition rate. It can be seen from the experiments in this paper that the performance of the implemented hardware is significantly better than that of existing research.

Implementation and evaluation of parallel FFT on Engineering and Scientific Computation Accelerator (ESCA) architecture

The fast Fourier transform (FFT) is a fundamental kernel of many computation-intensive scientific applications. This paper deals with an implementation of the FFT on the accelerator system, a heterogeneous multicore architecture to accelerate computation-intensive parallel computing in scientific and engineering applications. The Engineering and Scientific Computation Accelerator (ESCA) consists of a control unit and a single instruction multiple data (SIMD) processing element (PE) array, in which PEs communicate with each other via a hierarchical two-level network-on-chip (NoC) with high bandwidth and low latency. We exploit the architecture features of ESCA to implement a parallel FFT algorithm efficiently. Experimental results show that both the proposed parallel FFT algorithm and the ESCA architecture are scalable. The 16-bit fixed-point parallel FFT performance of ESCA is compared with a published work to prove the superiority of the mapping algorithm and the hardware architecture. The floating-point parallel FFT performances of ESCA are evaluated and compared with those of the IBM Cell processor and GPU to demonstrate the computing power of the ESCA system for high performance applications.

Novel algorithm for complex bit reversal: employing vector permutation and branch reduction methods

We present novel vector permutation and branch reduction methods to minimize the number of execution cycles for bit reversal algorithms. The new methods are applied to single instruction multiple data (SIMD) parallel implementation of complex data floating-point fast Fourier transform (FFT). The number of operational clock cycles can be reduced by an average factor of 3.5 by using our vector permutation methods and by 1.1 by using our branch reduction methods, compared with conventional implementations. Experiments on MPC7448 (a well-known SIMD reduced instruction set computing processor) demonstrate that our optimal bit-reversal algorithm consistently takes fewer than two cycles per element in complex array operations.