Floating-point Division Research Articles

Low-Power High Precision Floating-Point Divider With Bidimensional Linear Approximation

Low-Power High Precision Floating-Point Divider With Bidimensional Linear Approximation

Novel Low-Power Floating-Point Divider With Linear Approximation and Minimum Mean Relative Error

Novel Low-Power Floating-Point Divider With Linear Approximation and Minimum Mean Relative Error

Comparative study of single precision floating point division using different computational algorithms

<span>This paper presents different computational algorithms to implement single precision floating point division on field programmable gate arrays (FPGA). Fast division computation algorithms can apply to all division cases by which an efficient result will be obtained in terms of delay time and power consumption. 24-bit Vedic multiplication (Urdhva-Triyakbhyam-sutra) technique enhances the computational speed of the mantissa module and this module is used to design a 32-bit floating point multiplier which is the crucial feature of this proposed design, which yields a higher computational speed and reduced delay time. The proposed design of floating-point divider using fast computational algorithms synthesized using Verilog hardware description language has a 32-bit floating point multiplier module unit and a 32-bit floating point subtractor module unit. Xilinx Spartan 6 SP605 evaluation platform is used to verify this proposed design on FPGA. Synthesis results provide the device utilization and propagation delay parameters for the proposed design and a comparative study is done with previous work. Input to the divider is provided in IEEE 754 32-bit formats.</span>

Radix-64 Floating-Point Division and Square Root: Iterative and Pipelined Units

Digit-recurrence algorithms are widely used in actual microprocessors to compute floating-point division and square root. These iterative algorithms present a good trade-off in terms of performance, area and power. Traditionally, commercial processors have iterative division and square root units where the iteration logic is used over several cycles. The main drawbacks of these iterative units are long latency and low throughput due to the reuse of part of the logic over several cycles, and its hardware complexity with separated logic for division and square root. We present a radix-64 floating-point division and square root algorithm with a common iteration for division and square root and where, to have an affordable implementation, each radix-64 iteration is made of two simpler radix-8 iterations. The radix-64 algorithm allows to get low-latency operations, and the common division and square root radix-64 iteration results in some area reduction. The algorithm is mapped into two different microarchitectures: a low-latency and low area iterative unit, and a low-latency and high-throughput pipelined unit. In both units speculation between consecutive radix-8 iterations is used to reduce the timing.

Effective scheme of parity-preserving-reversible floating-point divider

Effective scheme of parity-preserving-reversible floating-point divider

Efficient Floating-point Division Quantum Circuit using Newton-Raphson Division

The development of quantum algorithms is facilitated by quantum circuit designs. A floating-point number can represent a wide range of values and is extremely useful in digital signal processing. A quantum circuit model to implement the floating-point division problem using the Newton-Raphson division algorithm is proposed in this paper. The proposed division circuit offers a significant savings in T-gates and qubits used in the circuit design when correlated with the state of art works proposed on fast division algorithms. The qubits savings are estimated around 17% and 20%, T-count savings are around 59.03% and 20.31%. Similarly, T-depth savings is estimated around 77.45% and 24.33% over the existing works.

An Energy-Efficient Approximate Divider Based on Logarithmic Conversion and Piecewise Constant Approximation

Approximate computing (AC) has been considered as a promising paradigm to improve the energy-efficiency of computing hardware for error-tolerant applications, with negligible quality degradation to the output. Dividers frequently limit the performance of a computing system; however, they have not received as much attention as multipliers and adders in AC. In this paper, an energy-efficient and high-performance approximate divider is proposed based on logarithmic conversion and piecewise constant approximation. In this design, the range for the conversion between binary and logarithmic numbers is first expanded from <inline-formula> <tex-math notation="LaTeX">$\mathbf {[{0,1}]}$ </tex-math></inline-formula> to <inline-formula> <tex-math notation="LaTeX">$\mathbf {[-0.5,1]}$ </tex-math></inline-formula>. A heuristic search algorithm is then devised to find the most accurate constant set to approximate the reciprocal of the divisor, by minimizing a statistical error. The hardware implementation is presented for both floating-point (FP) and integer dividers. With a high configurability, the proposed divider results in a mean relative error distance (MRED) from 2.78&#x0025; to 0.046&#x0025;, indicating a high accuracy among state-of-the-art approximate dividers. Compared to the half-precision FP divider, the proposed divider with a MRED of 0.74&#x0025; can achieve nearly <inline-formula> <tex-math notation="LaTeX">$\mathbf {90\times }$ </tex-math></inline-formula> improvement in PDP. Moreover, compared to state-of-the-art approximate dividers, the proposed design is in the Pareto Frontier in terms of power delay product (PDP) and MRED. The three image processing application results demonstrate that the proposed divider can result in the highest peak signal-to-noise ratio (PSNR) and structural similarity (SSIM) even with truncation.

Low-Latency Bit-Accurate Architecture for Configurable Precision Floating-Point Division

Floating-point division is indispensable and becoming increasingly important in many modern applications. To improve speed performance of floating-point division in actual microprocessors, this paper proposes a low-latency architecture with a multi-precision architecture for floating-point division which will meet the IEEE-754 standard. There are three parts in the floating-point division design: pre-configuration, mantissa division, and quotient normalization. In the part of mantissa division, based on the fast division algorithm, a Predict–Correct algorithm is employed which brings about more partial quotient bits per cycle without consuming too much circuit area. Detailed analysis is presented to support the guaranteed accuracy per cycle with no restriction to specific parameters. In the synthesis using TSMC, 90 nm standard cell library, the results show that the proposed architecture has ≈63.6% latency, ≈30.23% total time (latency × period), ≈31.8% total energy (power × latency × period), and ≈44.6% efficient average energy (power × latency × period/efficient length) overhead over the latest floating-point division structure. In terms of latency, the proposed division architecture is much faster than several classic processors.

T-Count Optimized Quantum Circuit Designs for Single-Precision Floating-Point Division

The implementation of quantum computing processors for scientific applications includes quantum floating points circuits for arithmetic operations. This work adopts the standard division algorithms for floating-point numbers with restoring, non-restoring, and Goldschmidt division algorithms for single-precision inputs. The design proposals are carried out while using the quantum Clifford+T gates set, and resource estimates in terms of numbers of qubits, T-count, and T-depth are provided for the proposed circuits. By improving the leading zero detector (LZD) unit structure, the proposed division circuits show a significant reduction in the T-count when compared to the existing works on floating-point division.

Design And Optimization Of Floating Point Division And Square Root Using Minimal Device Latency

New microprocessors have become a compulsory feature of floating-point support. In recent years, multiple generations of floating-point units (FPU’s) have been seen by leading architectures. Although the introduction of addition and multiplication has been increasingly effective, the support of division as well as square root will have remained uneven. The types of algorithms employed, as well as the quality and efficiency of the implementations, are drastically different. Here a floating-point division and square root unit is provided that implements a radix-64 floating-point division and a radix-16 floating-point squareroot. Here a floating-point division and square root unit is provided that implements a radix-64 floating-point division and aradix-16 floating-point squareroot. Speculation between successive radix-4 incarnations is used to achieve a reduced timing. In digit-recurrence implementations, there are three separate components: initialization, digital repeats, and rounding. The repetition of the digit is the iterative component and for multiple loops it follows the same logic. The initialization and rounding steps are partly shared by the division and square root, although each has a separate logic for digital iterations. The result is a floating-point divider and square root with low latency, requiring double, single S and half-precision division of standardized operandsand 11, 6, and 4 result cycles, and 15, 8, and 5 cycles of square root cycles. One or two additional cycles are required in the case S of subnormal operand(s) or result

An Architecture of Area-Effective High Radix Floating-Point Divider With Low-Power Consumption

In this paper, a novel architecture of area-effective high-radix floating-point divider with low power consumption is proposed. By extending the principle of the standard SRT algorithm, the divider can estimate the partial quotient digits by a simpler circuit and tolerate certain calculation errors in each recurrence cycle. In addition, the accumulation of errors in the recurrence process can be eliminated automatically without additional calculation cycle. The latency and area cost of the divider are linear with the radix number, which solves the problem that the quotient digits selection tables in high-radix divider have high area cost. Base on the proposed architecture a single-precision floating-point divider is implemented, which has an area of 6037.20 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu {\mathrm{ m}}^{2}$ </tex-math></inline-formula> in 65nm process. The dynamic power consumption of the divider is only 0.848mW at 250MHz. Compared with other dividers reported in the literature, the area cost can be reduced by about 90% with the same computation precision and performance.

A NOVEL QUOTIENT PREDICTION FOR FLOATING-POINT DIVISION

At present, floating-point operations are used as add-on functions in critical embedded systems, such as physics, aerospace system, nuclear simulation, image and digital signal processing, automatic control system and optimal control and financial, etc. However, floating-point division is slower than floating-point multiplication. To solve this problem, many existing works try to reduce the required number of iterations, which exploit large Look Up Table (LUT) resource to achieve approximate mantissa of a quotient. In this paper, we propose a novel prediction algorithm to achieve an optimal quotient by predicting certain bits in a dividend and a divisor, which reduces the required LUT resource. Therefore, the final quotient is achieved by accumulating all predicted quotients using our proposed prediction algorithm. The experimental results show that only 3 to 5 iterations are required to obtain the final quotient in a floating-point division computation. In addition, our proposed design takes up 0.84% to 3.28% (1732 LUTs to 6798 LUTs) and 5.04% to 10.08% (1916 (ALUT) to 3832 (ALUT)) when ported to Xilinx Virtex-5 and Altera Stratix-III FPGAs, respectively. Furthermore, our proposed design allows users to track remainders and to set customized thresholds of these remainders to be compatible with a specific application.

Floating-Point Calculations on a Quantum Annealer: Division and Matrix Inversion

Systems of linear equations are employed almost universally across a wide range of disciplines, from physics and engineering to biology, chemistry and statistics. Traditional solution methods such as Gaussian elimination become very time consuming for large matrices, and more efficient computational methods are desired. In the twilight of Moore\rq{}s Law, quantum computing is perhaps the most direct path out of the darkness. There are two complementary paradigms for quantum computing, namely, gated systems and quantum annealers. In this paper, we express floating point operations such as division and matrix inversion in terms of a {\em quadratic unconstrained binary optimization} (QUBO) problem, a formulation that is ideal for a quantum annealer. We first address floating point division, and then move on to matrix inversion. We provide a general algorithm for any number of dimensions, but we provide results from the D-Wave quantum anneler for 2x2 and 3x3 general matrices. Our algorithm scales to very large numbers of linear equations. We should also mention that our algorithm provides the full solution the the matrix problem, while HHL provides only an expectation value.

Low Latency Floating-Point Division and Square Root Unit

Digit-recurrence algorithms are widely used in actual microprocessors to compute floating-point division and square root. These iterative algorithms present a good trade-off in terms of performance, area and power. We present a floating-point division and square root unit, which implements a radix-64 floating-point division and a radix-16 floating-point square root. To have an affordable implementation, each radix-64 division iteration and radix-16 square root iteration are made of simpler radix-4 iterations: 3 radix-4 iterations in division and 2 in square root. Speculation is used between consecutive radix-4 iterations to get a reduced timing. There are three different parts in digit-recurrence implementations: initialization, digit iterations, and rounding. The digit iteration is the iterative part and it uses the same logic for several cycles. Division and square root share partially the initialization and rounding stages, whereas each one has different logic for the digit iterations. The result is a low-latency floating-point divider and square root, requiring 11, 6, and 4 cycles for double, single and half-precision division with normalized operands and result, and 15, 8 and 5 cycles for square root. One or two additional cycles are needed in case of subnormal operand(s) or result.

Implementation of high precision/low latency FP divider using Urdhva–Tiryakbhyam multiplier for SoC applications

The increasing demand of Industrial and Scientific data intensive applications are higher precision arithmetic with reduced computation time. In this paper, we designed a high-precision, fully pipelined 32-bit floating-point (FP) divider using Newton–Raphson (NR) algorithm realized with Urdhva–Tiryakbhyam (UT) multiplier for System on Chip applications. The divider design is based on Newton–Raphson (multiplicative) method and it supports all IEEE rounding modes with a latency of 15 cycles. The iterative NR computations are performed by using FP multiplier and FP adder. The key module of FP multiplier for calculating mantissa part is UT multiplier. It’s an ancient Vedic multiplication technique used from few centuries back for doing fast multiplications. We implemented two UT multipliers: one using carry look-ahead adders and another one using carry save adders. The results show that, the proposed architectures have 12% better precision with 24% high throughput than existing algorithms, at the cost of high on-chip power. The inputs to the divider are represented in IEEE-754 standard. The design uses Xilinx Vivado software and it is implemented on Virtex7 FPGA.

Study on Single Flux Quantum Floating-Point Divider Based on Goldschmidt's Algorithm

We investigate a Goldschmidt's single flux quantum (SFQ) floating-point divider that is suitable for the implementation using the bit-serial pipelined SFQ circuit. We designed the bit-serial SFQ divider that outputs the 11-bit quotient. The simulation results show correct operation at the frequency of 50-GHz and bias margin of 80%–125%. We also estimated dependence of latency and the number of Josephson junctions on accuracy of outputs. According to the estimation, double-precision SFQ divider can be designed using 27 000 Josephson junctions, which can be implemented on one chip using the current SFQ circuit fabrication technology. Because of the small circuit area and multiplier-based hardware architecture, the investigated divider can be applied to build an SFQ graphical processing unit.

Implementation of multi-precision floating point divider for high speed signal processing applications

The introduction of fused multiplier and add technique enhances design metrics of floating point (FP) arithmetic operations. Particularly Newton–Raphson (NR) based division algorithm is popular choice to SRT division algorithms. This paper proposes 32-bit FP division using NR computational division technique with pipelining method capable of doing high speed signal processing operations. The proposed divider used as IP core and make it as optimal choice to speed up FP operations. It improves rounding accuracy in addition with reduction in area overhead. The NR computational calculations are implemented by iteratively using 32-bit FP multiplier and adder. The key module used for calculating significand (mantissa) part is 24-bit Wallace tree multiplier using carry save adders. The Wallace multiplier provides higher computational speed, hence, is effectively utilized as a part of FP divider. The proposed pipelined FP divider is fully combinational circuit with clock and data gating applied to reduce the dynamic power consumption, delay and area overhead designed for signal processing applications. It also improves the accuracy of the result. The operands are represented and operated using IEEE 754 standard. The operation and results are validated through simulation using VIVADO software and implemented on Xilinx-7 series, ARTIX field programmable gate array.

Different modified zeroing neural dynamics with inherent tolerance to noises for time-varying reciprocal problems: A control-theoretic approach

With reciprocal problem widely arising in various scientific computation and engineering fields in recent decades, it is always assumed that the computing process is free of measurement noises. However, time is precious for time-varying reciprocal problem, which is considered to be an important operation in a floating-point divider in practice and optimization. Therefore, mathematical models with inherent noise tolerance are needed to compute reciprocal problem in real time. In this paper, different modified zeroing neural dynamics models are proposed, analyzed and investigated for the solution of time-varying reciprocal problem with inherent tolerance to noises. Moreover, theoretical analyses show that the modified zeroing neural dynamics globally/exponentially converge to the exact solution of the time-varying reciprocal problem with measurement noises. Furthermore, the zeroing neural dynamic models with different activation functions are employed for comparison with the modified zeroing neural dynamic model. Finally, some numerical simulations are reported and analyzed to substantiate the feasibility and superiority of the developed zeroing neural dynamic for time-varying reciprocal problem with inherent tolerance to noises. This paper develops a systematic approach on exploiting control techniques to design zeroing neural dynamic models for robustly and accurately solving time-varying reciprocal problems.

Efficient Floating-Point Division for Digital Signal Processing Application [Tips &amp; Tricks

Floating-point division is an expensive operation for processors in digital signal processing (DSP). The basis of the division operation is finding the reciprocal of the divisor. We present a reciprocal algorithm with four multiplications for single accuracy and six for double accuracy. The algorithm specifically includes bithack (known as magic constant) operations and floating-point addition, multiplication, and the fused multiply-add (fma) operation. The proposed approach improves two characteristics of the division process: accuracy and number of steps. This second characteristic has a direct impact on the division operation performance time and on the amount of equipment required for hardware implementation.

Design and Synthesis of Restoring Technique Based Dual Mode Floating Point Divider for Fast Computing Applications

Floating point division plays a vital role in quick processing applications. A division is one amongst the complicated modules needed in processors. Area, delay and power consumption are the main factors that play a significant role once planning a floating point dual-precision divider. Compared to different floating-point arithmetic, the design of division is way a lot of sophisticated and needs longer time. Floating point division is that the main arithmetic unit that is employed within the design of the many processors in the field of DSP, math processors and plenty of different applications. This paper relies on the dual-mode practicality of floating point division. The proposed designed architecture supports the single precision (32-bit) as well as double precision (64-bit) IEEE 754 floating point format. It uses restoring division technique for the fraction part division. This design consists of varied sub-modules like shifters, exceptional handlers, Normalizers and many more.