Floating-point Arithmetic Operations Research Articles

Hybrid Precision Floating-Point (HPFP) Selection to Optimize Hardware-Constrained Accelerator for CNN Training.

The rapid advancement in AI requires efficient accelerators for training on edge devices, which often face challenges related to the high hardware costs of floating-point arithmetic operations. To tackle these problems, efficient floating-point formats inspired by block floating-point (BFP), such as Microsoft Floating Point (MSFP) and FlexBlock (FB), are emerging. However, they have limited dynamic range and precision for the smaller magnitude values within a block due to the shared exponent. This limits the BFP's ability to train deep neural networks (DNNs) with diverse datasets. This paper introduces the hybrid precision (HPFP) selection algorithms, designed to systematically reduce precision and implement hybrid precision strategies, thereby balancing layer-wise arithmetic operations and data path precision to address the shortcomings of traditional floating-point formats. Reducing the data bit width with HPFP allows more read/write operations from memory per cycle, thereby decreasing off-chip data access and the size of on-chip memories. Unlike traditional reduced precision formats that use BFP for calculating partial sums and accumulating those partial sums in 32-bit Floating Point (FP32), HPFP leads to significant hardware savings by performing all multiply and accumulate operations in reduced floating-point format. For evaluation, two training accelerators for the YOLOv2-Tiny model were developed, employing distinct mixed precision strategies, and their performance was benchmarked against an accelerator utilizing a conventional brain floating point of 16 bits (Bfloat16). The HPFP selection, employing 10 bits for the data path of all layers and for the arithmetic of layers requiring low precision, along with 12 bits for layers requiring higher precision, results in a 49.4% reduction in energy consumption and a 37.5% decrease in memory access. This is achieved with only a marginal mean Average Precision (mAP) degradation of 0.8% when compared to an accelerator based on Bfloat16. This comparison demonstrates that the proposed accelerator based on HPFP can be an efficient approach to designing compact and low-power accelerators without sacrificing accuracy.

Multi-image super-resolution based low complexity deep network for image compressive sensing reconstruction

Deep learning (DL) has been widely utilized in image compressive sensing (CS) to enhance the quality and speed of reconstruction. The typical deep network for CS reconstruction comprises an initial reconstruction subnetwork, followed by a cascaded deep refinement reconstruction subnetworks. This paper introduces a new low-complexity image CS deep reconstruction framework, GSRCS, which leverages multi-image based deep super-resolution technology to better address the cost constraints of practical applications. The proposed initial reconstruction module generates multiple low-resolution images in parallel by grouping the input measurements, while a high-quality, high-resolution reconstructed image is produced through a multi-image deep super-resolution network. The theoretical derivation and experimental results demonstrate that this method significantly reduces system complexity in terms of parameters and floating-point arithmetic operations, while achieving competitive reconstruction performance compared to the state-of-the-arts. Specifically, the average number of parameters is reduced by over 63%, and the computational complexity is decreased by more than 88%.

Optimization of re-configurable multi-core processors and security based on field programmable gate arrays

<div align="center">n system-on-a-chip based complex processors has the problem of multithreading and miss-functionality due to their complexity and high-speed operations. In order to minimize these problems, the proposed design has machine learning based algorithms and cryptography systems for security has been incorporated. In the proposed work, the security level has been taken care of in three different stages such as data integrity, data authentication, and private and public keys encryption and decryption. In order to increase throughput with minimal latency, the proposed architecture with advanced high-performance protocol and advanced high-performance and advanced peripheral bus bridge is incorporated between the fabric dynamically re configurable multi-processor and peripherals along with security algorithms using secure hash algorithm (SHA-256) bits and advanced encryption standard (AES). In order to perform machine learning based applications, the proposed system is incorporated double-precision floating point arithmetic operations. The overall proposed architecture is developed in verilog hybrid deep learning (HDL) and quality checking using the LINT tool. The entire design is interfaced with the Zynq processor and software development kit (SDK) tool to verify data transfer between hardware and software. The obtained results are compared with existing state-of-art results and found that 18% improvement in throughput, a 21% improvement in power consumption savings, and a 34% reduction in latency.</div>

Max-C and Min-D Projection Auto-Associative Fuzzy Morphological Memories: Theory and an Application for Face Recognition

Max-C and min-D projection auto-associative fuzzy morphological memories (max-C and min-D PAFMMs) are two-layer feedforward fuzzy morphological neural networks designed to store and retrieve finite fuzzy sets. This paper addresses the main features of these auto-associative memories: unlimited absolute storage capacity, fast retrieval of stored items, few spurious memories, and excellent tolerance to either dilative or erosive noise. Particular attention is given to the so-called Zadeh’ PAFMM, which exhibits the most significant noise tolerance among the max-C and min-D PAFMMs besides performing no floating-point arithmetic operations. Computational experiments reveal that Zadeh’s max-C PFAMM, combined with a noise masking strategy, yields a fast and robust classifier with a strong potential for face recognition tasks.

An efficient design methodology to speed up the FPGA implementation of artificial neural networks

In this paper, we propose and formulate a C++ based training methodology for speeding up the implementation of an Artificial Neural Network (ANN) in a Field Programmable Gate Array (FPGA). The proposed ANN implementation methodology uses a custom C++ based program referred to as Neural Network Design Parameter Extraction (NNDPE) program developed using an open source library namely Fast Artificial Neural Network (FANN). The proposed C++ based NNDPE program reduces the time required to train and extract the design parameters of the ANN, such as the number of layers, the number of neurons in each layer, and the weights. The extracted ANN design parameters, custom hardware arithmetic units, and function-approximate activation functions are used to implement the ANN hardware architecture of a linear function on the Virtex-7 FPGA platform. The Vivado 2018.3 tool is used to simulate, synthesize, and implement the ANN-based linear function. It was concluded from the simulation that the ANN hardware implementation has high precision due to the usage of floating-point arithmetic operations compared to the ANN which uses fixed-point arithmetic operations. The ANN-implemented on the Virtex-7 FPGA operates at 150.76 MHz, which is approximately 11 to 18 times faster than the software implementation running on various CPU cores with operating frequencies ranging over 2.2 GHz to 4.70 GHz.

High-speed binary coded decimal digit multipliers with multiple error detection

Decimal arithmetic in the form of binary coded decimal (BCD) numbers is preferred in many financial, commercial and scientific applications. BCD multipliers are introduced as a key hardware unit to support both integer and floating-point decimal arithmetic operations. However, due to the increasing sensitivity of VLSI-based digital designs to the environmental effects, BCD multipliers are also prone to faults and errors similar to other arithmetic circuits. In addition, multiple error occurrence is possible in current digital systems especially in space applications which motivates to reach multiple error detection/correction in addition to single errors. In this paper, digit-by-digit BCD multipliers are introduced capable of multiple error detection with low delay overheads. To show the effectiveness of the proposed combined method, a 4-digit BCD multiplier is presented. Experimental results based on analysis and error injection-based simulations show that in addition to 100% single error detection, multiple errors can be detected with at least 99.6% probability in the 4-digit BCD multiplier as the implemented architecture.

An exa-scale high-performance molecular dynamics simulation program: MODYLAS.

A new version of the highly parallelized general-purpose molecular dynamics (MD) simulation program MODYLAS with high performance on the Fugaku computer was developed. A benchmark test using Fugaku indicated highly efficient communication, single instruction, multiple data (SIMD) processing, and on-cache arithmetic operations. The system's performance deteriorated only slightly, even under high parallelization. In particular, a newly developed minimum transferred data method, requiring a significantly lower amount of data transfer compared to conventional communications, showed significantly high performance. The coordinates and forces of 101 810 176 atoms and the multipole coefficients of the subcells could be distributed to the 32 768 nodes (1 572 864 cores) in 2.3ms during one MD step calculation. The SIMD effective instruction rates for floating-point arithmetic operations in direct force and fast multipole method (FMM) calculations measured on Fugaku were 78.7% and 31.5%, respectively. The development of a data reuse algorithm enhanced the on-cache processing; the cache miss rate for direct force and FMM calculations was only 2.74% and 1.43%, respectively, on the L1 cache and 0.08% and 0.60%, respectively, on the L2 cache. The modified MODYLAS could complete one MD single time-step calculation within 8.5ms for the aforementioned large system. Additionally, the program contains numerous functions for material research that enable free energy calculations, along with the generation of various ensembles and molecular constraints.

Implementation of Pipelined Multi_Precision (1, 2 and 4) Floating-point Arithmetic Operations

Abstract: The implementation of pipelined multi-precision-based arithmetic operations are carried out. In the existing system, the floating-point operation is based on single precision and is implemented on a divider. The proposed design has been implemented using single, double and quad precision using the universal piece-wise linear (PWL) approximation method and a modified Goldschmidt algorithm. The proposed design performs addition, subtraction, multiplication, and division using the universal PWL method to reduce maximum error. Small multipliers are used in the modified Goldschmidt algorithm. The pipelining process has been used in order to improve the speed of execution and accuracy. This pipelined architecture is described in Verilog and timing performance is measured with Xilinx timing analyser.

Vibration compensation of delta 3D printer with position-varying dynamics using filtered B-splines

The delta robot can reach higher speeds than traditional serial-axis machines used in fused filament fabrication 3D printing. However, like serial machines, delta printers suffer from undesirable vibration at high speeds which degrades the quality of fabricated parts. This undesirable vibration has been suppressed in serial printers using linear model-inversion feedforward control methods like the filtered B-splines (FBS) approach. However, techniques like the FBS approach are computationally challenging to implement on delta 3D printers because of their coupled, position-dependent dynamics. In this paper, we propose a methodology to address the computational bottlenecks by (1) parameterizing the position-dependent portions of the dynamics offline to enable efficient computation of the model online, (2) computing models at sampled points (instead of every point) along the given trajectory, and (3) employing QR factorization to reduce the number of floating-point arithmetic operations associated with matrix inversion. In simulations, we report a computation time reduction of up to 23× using the proposed method when compared to using the computationally expensive exact LPV model—all while maintaining high tracking accuracy. Accordingly, we demonstrate significant quality improvements on parts printed at various positions on a commercial delta 3D printer using our proposed controller compared to a baseline alternative, which uses an LTI model from one position. Acceleration measurements during printing show that the improvement in print quality of the proposed controller is due to vibration reductions of up to 39% when compared to the baseline controller.

Enabling In-Network Floating-Point Arithmetic for Efficient Computation Offloading

Programmable switches are recently used for accelerating data-intensive distributed applications. Some computational tasks, traditionally performed on servers in data centers, are offloaded into the network on programmable switches. These tasks may require the support of on-the-fly floating-point operations. Unfortunately, programmable switches are restricted to simple integer arithmetic operations. Existing systems circumvent this restriction by converting floats to integers or relying on local CPUs of switches, incurring extra processing delayed and accuracy loss. To address this gap, we propose NetFC, a table-lookup method to achieve on-the-fly in-network floating-point arithmetic operations nearly without accuracy loss. Specifically, NetFC utilizes logarithm projection and transformation to convert the original huge table enumerating all operands and results into several much smaller tables that can fit into the data plane of programmable switches. To cope with the table inflation problem on 32-bit floats, we also propose an approximation method that further breaks the large tables into smaller ones. In addition, NetFC leverages two optimizations to improve accuracy and reduce on-chip memory consumption. We use both synthetic and real-life datasets to evaluate NetFC. The experimental results show that the average accuracy of NetFC is above 99.9% with only 448KB memory consumption for 16-bit floats and 99.1% with 496KB memory consumption for 32-bit floats. Furthermore, we integrate NetFC into two distributed applications and two in-network telemetry systems to show its effectiveness in further improving the performance.

Increasing the sensitivity of real-time method for diagnostic of autogenerators phase synchronization based on their non-stationary time series

Purpose of this work is to of the research – Increasing the sensitivity of a method for diagnosing phase synchronization of autogenerators based on their non-stationary time series in real time, and also a comparison of the statistical properties of the proposed modification of the method with the well-known method for diagnostics of loop synchronization, which has proven itself in the analysis of experimental data. Methods.The paper compares the probabilities of the appearance of an error of the second kind of the developed modified method for diagnostics of phase synchronization with the probabilities of occurrence of an error of the second kind of the known method at equal values of sensitivity. When comparing the methods, generated test time realizations with a priori known boundaries of the phase synchronization sections are used, which repeat the statistical properties of the experimental data. It also compares the computational complexity of the two methods. Results. A modification of the method for diagnosing phase synchronization of autonomic regulation circuits in real time is proposed. It is shown that the proposed modification provides similar values of sensitivity and probability of appearance of errors of the second kind as the previously proposed approach. The developed method has less computational complexity than the previously proposed method. The values of free parameters corresponding to different values of sensitivity and probability of appearance of errors of the second kind are obtained. Conclusion. The area of application of the developed method with modification is formulated. The low computational complexity of the proposed method, as well as the possibility of switching devices to integer computations in calculations, makes it possible to use it for wearable registrations performing calculations in real time, based on small-sized low-power processors that do not support floating-point arithmetic operations.

Parallel GPF solution: A GPU‐CPU‐based vectorization parallelization and sparse technique for NR implementation

As an essential simulation tool, global power flow (GPF) can approximately model mutual impacts of interactions between transmission system (TS) and distribution system (DS). However, sequential GPF lacks timely solution performance required in several applications built on top of GPF, for example, contingency analysis. To address this issue, graphic processing unit (GPU) with excellent floating-point arithmetic operations is introduced and in turn a Master-Slave-Splitting (MSS) based parallel GPF approach is proposed via vectorization parallelization under GPU-CPU heterogeneous architecture. First, the root cause behind sparsity property of GPF and its impacts on key steps of NR-based GPF approach are quantitatively analysed. Considering the studies carried out in the authors' previous work of the application of GPU and sparse techniques on TS power flow (TS-PF), its applications on parallel implementations of corresponding steps engaged in three-phase imbalanced DS power flow (DS-PF) is mainly focused on. Numerical studies validate the effects of various custom-designed parallel schemes on acceleration enhancement of individual steps in the proposed GPU-CPU parallel GPF approach.

Rigorous Lower Bounds for the Ground State Energy of Molecules by Employing Necessary N-Representability Conditions.

Electronic structure calculations, in particular the computation of the ground state energy, lead to challenging problems in optimization. These problems are of enormous importance in quantum chemistry for calculations of properties of solids and molecules. Minimization methods for computing the ground state energy can be developed by employing a variational approach, where the second-order reduced density matrix defines the variable. This concept leads to large-scale semidefinite programming problems that provide a lower bound for the ground state energy. Upper bounds of the ground state energy can be calculated for example with the Hartree-Fock method or numerically more exact for a given basis set by full CI. However, Nakata et al. ( J. Chem. Phys.200111482828292) observed that due to numerical errors the semidefinite solver produced erroneous results with a lower bound significantly larger than the full CI energy. For the LiH, CH-, NH-, OH, OH-, and HF molecules violations within one mhartree were observed. We applied the software VSDP which takes all numerical errors due to floating-point arithmetic operations into consideration. For two test libraries VSDP provides tight rigorous error bounds lower than full CI energies reported with an accuracy of 0.1 to 0.01 mhartree. Only little computation work must be spent in order to compute close rigorous error bounds for the ground state energy.

A multi-GPU implementation of a full-field crystal plasticity solver for efficient modeling of high-resolution microstructures

In a recent publication (Eghtesad et al., 2018), we have reported a message passing interface (MPI)-based domain decomposition parallel implementation of an elasto-viscoplastic fast Fourier transform-based (EVPFFT) micromechanical solver to facilitate computationally efficient crystal plasticity modeling of polycrystalline materials. In this paper, we present major extensions to the previously reported implementation to take advantage of graphics processing units (GPUs), which can perform floating point arithmetic operations much faster than traditional central processing units (CPUs). In particular, the applications are developed to utilize a single GPU and multiple GPUs from one computer as well as a large number of GPUs across nodes of a supercomputer. To this end, the implementation combines the OpenACC programming model for GPU acceleration with MPI for distributed computing. Moreover, the FFT calculations are performed using the efficient Compute Unified Device Architecture (CUDA) FFT library, called CUFFT. Finally, to maintain performance portability, OpenACC-CUDA interoperability for data transfers between CPU and GPUs is used. The overall implementations are termed ACC-EVPCUFFT for single GPU and MPI-ACC-EVPCUFFT for multiple GPUs. To facilitate performance evaluation studies of the developed computational framework, deformation of a single phase copper is simulated, while to further demonstrate utility of the implementation for resolving fine microstructures, deformation of a dual-phase steel DP590 is simulated. The implementations and results are presented and discussed in this paper.

STUDY AND ANALYSIS OF REMOTE SENSING DATA PARALLEL PROCESSING

Abstract. This paper analyzes a varieties of procedure of remote sensing data processing, and explores the common mathematical models, common algorithm models, and public function processing units of data processing shared by different tasks or even different parts within an individual task. Public modules are established to improve the parallelism of remote sensing data processing based on FPGA, which has excellent parallel processing performance. In addition, in order to reduce the resource consumption and increase the calculation efficiency of the designed FPGA program, the method of avoiding floating-point arithmetic and division operation in FPGA programming are discussed in this paper. There are a large number of common calculation modules between different tasks, such as the rotation matrix calculation module in attitude solution, geometric correction, and orthorectification task. Image preprocessing, feature information extraction, image threshold separation, and connected region markers are all common processing modules for a target detection task. In the same task, there is also a common calculation module. When using the FPGA design program, the power series of 2 can be used to convert the floating-point operation to fixed-point operation with an acceptable precision. A similar approach can transform the division operation into multiplication and shift operations, thereby improve the computational performance of FPGA programming.

Resource Efficient Single Precision Floating Point Multiplier Using Karatsuba Algorithm

In floating point arithmetic operations, multiplication is the most required operation for many signal processing and scientific applications. 24-bit length mantissa multiplication is involved to obtain the floating point multiplication final result for two given single precision floating point numbers. This mantissa multiplication plays the major role in the performance evaluation in respect of occupied area and propagation delay. This paper presents the design and analysis of single precision floating point multiplication using karatsuba algorithm with vedic multiplier with the considering of modified 2x1 multiplexers and modified 4:2 compressors in order to overcome the drawbacks in the existing techniques . Further , the performance analysis of single precision floating point multiplier is analyzed in terms of area and delay using Karatsuba Algorithm with different existing techniques such as 4x1 multiplexers and 3:2 compressors and modified techniques such as 2x1 multiplexers, 4:2 compressors. From the simulation results, it is observed that single precision floating point multiplication with karatsuba algorithm using modified 4:2 compressor with XOR-MUX logic provides better performance with efficient usage of resources such as area and delay than that of existing techniques. All the blocks involved for floating point multiplication are coded with Verilog and synthesized using Xilinx ISE Simulator.

Resource Efficient Single Precision Floating Point Multiplier Using Karatsuba Algorithm

In floating point arithmetic operations, multiplication is the most required operation for many signal processing and scientific applications. 24-bit length mantissa multiplication is involved to obtain the floating point multiplication final result for two given single precision floating point numbers. This mantissa multiplication plays the major role in the performance evaluation in respect of occupied area and propagation delay. This paper presents the design and analysis of single precision floating point multiplication using karatsuba algorithm with vedic multiplier with the considering of modified 2x1 multiplexers and modified 4:2 compressors in order to overcome the drawbacks in the existing techniques . Further , the performance analysis of single precision floating point multiplier is analyzed in terms of area and delay using Karatsuba Algorithm with different existing techniques such as 4x1 multiplexers and 3:2 compressors and modified techniques such as 2x1 multiplexers, 4:2 compressors. From the simulation results, it is observed that single precision floating point multiplication with karatsuba algorithm using modified 4:2 compressor with XOR-MUX logic provides better performance with efficient usage of resources such as area and delay than that of existing techniques. All the blocks involved for floating point multiplication are coded with Verilog and synthesized using Xilinx ISE Simulator.

Data-Driven Background Subtraction Algorithm for In-Camera Acceleration in Thermal Imagery

Detection of moving objects in videos is a crucial step towards successful surveillance and monitoring applications. A key component for such tasks is called background subtraction and tries to extract regions of interest from the image background for further processing or action. For this reason, its accuracy and real-time performance is of great significance. Although, effective background subtraction methods have been proposed, only a few of them take into consideration the special characteristics of thermal imagery. In this work, we propose a background subtraction scheme, which models the thermal responses of each pixel as a mixture of Gaussians with unknown number of components. Following a Bayesian approach, our method automatically estimates the mixture structure, while simultaneously it avoids over/under fitting. The pixel density estimate is followed by an efficient and highly accurate updating mechanism, which permits our system to be automatically adapted to dynamically changing operation conditions. We propose a reference implementation of our method in reconfigurable hardware achieving both adequate performance and low power consumption. Adopting a High Level Synthesis design, demanding floating point arithmetic operations are mapped in reconfigurable hardware; demonstrating fast-prototyping and on-field customization at the same time.

Analysis of the precision problem in numerical calculation of the reliability indices of technical systems by the topological method at application of the floating-point arithmetic

This paper deals with the problem of precision error arising in numerical calculation of the reliability indices of technical systems by the topological method at application of the floating-point arithmetic. The topological method for calculation of the reliability indices in accordance with the reliability models based on the Markov chains is discussed. An example of correct calculation of the reliability indices on the basis of analytical derivation of calculating formulas and substitution of the initial reliability parameters into them is given. The floating-point types and arithmetic supported in hardware by the modern computers and examples of the precision loss in floating-point arithmetic operations are also observed. Finally, an example of incorrect calculation of the reliability indices, based on the numerical solving of the system of linear algebraic equations, using the floating-point arithmetic is also given.

Optimized Fundamental Signal Processing Operations For Energy Minimization on Heterogeneous Mobile Devices

Numerous signal processing applications are emerging on both mobile and high-performance computing systems. These applications are subject to responsiveness constraints for user interactivity and, at the same time, must be optimized for energy efficiency. The increasingly heterogeneous power-versus-performance profile of modern hardware introduces new opportunities for energy savings as well as challenges. In this line, recent systems-on-chip (SoC) composed of low-power multicore processors, combined with a small graphics accelerator (or GPU), yield a notable increment of the computational capacity while partially retaining the appealing low power consumption of embedded systems. This paper analyzes the potential of these new hardware systems to accelerate applications that involve a large number of floating-point arithmetic operations mainly in the form of convolutions. To assess the performance, a headphone-based spatial audio application for mobile devices based on a Samsung Exynos 5422 SoC has been developed. We discuss different implementations and analyze the tradeoffs between performance and energy efficiency for different scenarios and configurations. Our experimental results reveal that we can extend the battery lifetime of a device featuring such an architecture by a 238% by properly configuring and leveraging the computational resources.