Floating Guard Ring Research Articles

Design and fabrication of planar guard ring termination for high-voltage SiC diodes

An optimized multiple floating guard ring structure is investigated for the first time as an edge termination method for high voltage 4H-SiC planar devices. Simulations were performed to investigate SiC guard ring termination, and determine the optimum guard ring spacing for planar diodes with up to four floating rings. Simulated optimized designs predicted breakdown values from 40% of the ideal breakdown with a single ring, to 84% of the ideal value for diodes with four rings. Implanted 4H-SiC pn diodes with optimized guard ring designs were fabricated and results correlated to simulation. Experimental breakdown values of 1.2–1.3 kV for guard ring structure with four rings were in good agreement with simulated results.

Simulation and Fabrication of High-Voltage 4H-SiC Diodes with Multiple Floating Guard Ring Termination

Simulation and Fabrication of High-Voltage 4H-SiC Diodes with Multiple Floating Guard Ring Termination

Floating guard rings as high-voltage termination structures for radiation-tolerant silicon detectors

Multiple floating guard ring designs have been optimised for high-voltage operation of silicon X-ray detectors and microstrip detectors at hadron colliders. They have been processed on both single- and double-sided devices. Results are presented on their performance before and after being subjected to both ionising and non-ionising irradiation.

Micro-discharge noise and radiation damage of silicon microstrip sensors

We have examined experimentally some existing ideas for improving the radiation hardness of silicon microstrip sensors. We confirm that the extended electrode and the deep implant-strip proposed on the basis of simulation studies works effectively to suppress micro-discharge as well as junction breakdown of the bias or guard ring. For an integrated coupling capacitor a double layer structure of SiO 2 and Si 3N 4 provides better radiation hardness than that of single SiO 2 coupling in our design conditions. The onset voltage of the micro-discharge on the bias/guard ring has been studied for an extended electrode and a floating guard ring.

Potential measurements on floating-field-limiting rings in a power MOSFET by an electron beam probe

Potentials on the floating guard rings in a power vertical-channel double-diffused MOS(VDMOS) transistor were measured for the first time using an electron-beam probing system which incorporates a hemispherical retarding field energy analyser. Problems in measuring the potential on the VDMOS by an electron beam probe are that strong local fields on the specimen cause the primary electron beam to shift from the target position and depress the saturation level of the S curve due to formation of a potential barrier in front of the specimen. In the measurement procedure the primary electron beam shift is corrected by measuring the shift each time an experimental condition is changed. The influence of depression in the saturation level of the S curve is eliminated by setting the slice level of the S curve at a low level of less than the maximum depressed saturation level. Measured results well reflect the function of the floating guard ring structure.

A planar InP/InGaAs avalanche photodiode with floating guard ring and double diffused junction

The authors discuss the fabrication, performance, and design of a novel, planar In/sub 0.53/Ga/sub 0.47/ As/InP separate absorption and multiplication region avalanche photodiode (SAM-APD) with floating guard rings and a double Zn diffused junction. The APD, grown by both vapor phase epitaxy and metalorganic vapor phase epitaxy, is observed to have a uniform gain of 85, a minimum primary dark current density of 5*10/sup -6/ A/cm/sup 2/ at 90% of breakdown, and a capacitance of 0.4 pF for a front-side illuminated device. Both experimental and analytical results show that the double-diffused floating guard ring structure prevents edge breakdown, and also greatly reduces the electric field along the semiconductor/insulator surface. The operation mechanisms and the optimum design of the planar APD based on a two-dimensional device model are discussed. >

An analysis for the potential of floating guard rings

Analytical expressions are derived for the potential of a floating guard ring (FGR) which is placed in the vicinity of a reverse-biased planar p +- n junction fabricated on a lightly-doped epitaxial layer. Both the non-punchthrough case and the punchthrough case are considered. The expressions can be extended to the case with multiple rings. The derivation is based on the concept of the equi-potential line which has the same potential as the floating ring. Two-dimensional simulations using BAMBI show that our analytic equations are simple and accurate enough to be used for optimum design of floating guard rings.

Probing the minority-carrier quasi-Fermi level in epitaxial Schottky-barrier diodes

An experimental technique for probing the minority-carrier quasi-Fermi level in epitaxial Schottky-barrier diodes has been developed and verified for the first time. The technique uses a novel self-aligned floating guard ring as a probe for the hole quasi-Fermi level in the quasi-neutral epitaxial region of an epitaxial Schottky-barrier diode [1]. The anode of the Schottky diode is separated from the guard ring by a thin sidewall oxide, thereby allowing the guard ring to be electrically isolated from the anode. It is shown through both simple physical arguments and two-dimensional numerical simulations that the potential on the floating guard ring assumes the value of the plateau of constant-hole quasi-Fermi level in the quasi-neutral epitaxial region under the anode when bias is applied to the anode. Experimental measurements on both low- and high-barrier Schottky diodes agree very well with two-dimensional numerical simulations as well as computer simulations of a detailed equivalent-circuit model. The result provides direct evidence of the fact that the hold quasi-Fermi level in the silicon does not line up with the metal level at large forward bias and indicates that Schottky-barrier diodes can be scaled further than previously predicted.

Analytical expression for the potential of guard rings of diodes operating in the punchthrough mode

An analytical modeling is given to prove that the potential of the floating guard ring varies linearly versus the reverse applied bias in planar punch through diodes with one ring. The result is valid for multiple guard-ring structures. From this modeling and using the criterion of simultaneous breakdown on the main junction and on the rings for a given structure, an approximate and quick determination of the optimized ring spacings is obtained.

A Schottky-barrier diode with self-aligned floating guard ring

A Schottky-barrier diode with self-aligned floating guard ring is described. The device structure requires no additional mask or process step in an advanced bipolar LSI technology featuring polysilicon base contact and self-aligned emitter region [1]. In contrast to conventional guard ring structures, the guard ring is separated from the anode by a sidewall oxide of thickness less than 0.3 µm, allowing independent access to the guard ring. Near-ideal <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I-V</tex> characteristics are obtained. It is shown that the guard ring can be left floating without degrading the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I-V</tex> characteristics of the Schottky diode. In this mode of operation, the advantage of the guard ring is maintained while the depletion capacitance and charge storage due to minority-carrier injection from the p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -n junction which reduce the effectiveness of the Schottky diode as an antisaturation device are eliminated.