Floating Gate Defects Research Articles

A new BICS for CMOS operational amplifiers by using oscillation test techniques

In this paper, we present a built-in current sensor to test operational amplifiers that takes advantage of previous results where the negative supply current has been taken as the test observable using the Oscillation-test technique. The sensor is applied to a variable-length chain of OTAs considering an exhaustive analysis of catastrophic defects (opens, shorts), Gate Oxide Short and Floating Gate defects. We analyse the sensitivity of both frequency and amplitude of the current consumption. Results show that the proposed sensor provides 97% fault coverage, as the previous results suggested.

Characterization of Floating Gate Defects in Analog Cells

A unified approach to tackle the characterization of the floating gate defect in analog and mixed-signal circuits is introduced. An electrical level model of the defective circuit is proposed extending previous models used effectively in the digital domain. The poly-bulk, poly-well, poly-power rail and metal-poly capacitances are significant parameters in determining the behavior of the floating gate transistor. The model is used to analyze the feasibility of testing a simple analog cell with the floating gate defects through the observation of the quiescent current consumption and the dynamic behavior.

Current Testing of CMOS Combinational Circuits with Single Floating Gate Defects

The behavior of basic CMOS combinational gates in the presence of a floating gate defect is characterized in order to investigate its detectability by IDDQ . The defect is modeled at the circuit level by the poly-bulk and metal-poly capacitances, which determine the quiescent power supply current consumption (IDDQ ) of the defective circuit. The testing implications on the type of defective gate are studied. Experimental measures have been made on basic CMOS combinational modules designed with intentional floating gate defects. A good agreement is observed between the simulation results and the experimental data. A conventional ATPG for stuck-at faults is used to obtain the required exciting vector to test the floating gate defects by IDDQ Testing.

IDDQ testing of single floating gate defects using a two-pattern vector

Intermediate voltages may appear at the output of a gate in the presence of single floating gate defects. Propagation of the effect of the intermediate voltage to driven gate(s) allows detection of the defect by sensing the increase in IDDQ consumption downstream in the circuit. The mechanisms responsible for the intermediate voltages are modelled, and, experimental measurements on circuits fabricated with the defect are found to be consistent with the proposed model and analysis.

Electrical model of the floating gate defect in CMOS ICs: implications on I/sub DDQ/ testing

The behavior of an MOS transistor with an open in the polygate path (floating transistor gate defect) is investigated and its effect on the quiescent power supply current I/sub DDQ/ is studied. The possible detection of this defect by current testing is explored in fully complementary CMOS circuits. The behavior of a transistor with its floating gate is modeled using the coupling capacitances in the floating gate and the charge in the transistor gate. The poly-bulk and metal-poly capacitances are found to be two significant parameters in determining the degree of conduction on the affected transistor. The induced voltage in the floating gate and the quiescent current are estimated by analytical expressions. The model is compared with SPICE 2 simulations. Good agreement is observed between the simple analytical expressions, simulations and experimental measures performed on defective circuits. In addition, it is shown that the floating gate transistor can be modeled as a weakly conductive stuck-on transistor or as a stuck-open transistor depending on the values of the parameters characterizing the defect.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Logic testability of defective floating gate CMOS latches

The behaviour of a defective CMOS latch cell with floating gate defects is analysed in order to investigate the detection of these defects by logic testing. A large number (40%) of the defects will never be detectable by logic testing. Some of the remaining floating gate defects are also undetectable by logic testing, depending on their defect topologies. The need for other test methods such as IDDQ or delay testing is discussed.