Floating Diffusion Research Articles

High Sensitivity Dynamic Range Enhanced Complementary Metal–Oxide–Semiconductor Imager with Noise Suppression

In a high sensitivity complementary metal–oxide–semiconductor (CMOS) image sensor featuring a high conversion gain floating diffusion (FD) with a lateral overflow integration capacitor (LOFIC) in a pixel, the methods of the feedback noise suppression and the FD dark current reduction are discussed. The noise floor is found to be suppressed by introducing a small FD capacitance with the reduced feedback capacitance of a pixel source follower in accordance with a noise feedback theory. The reduction of the full well capacity due to the small FD capacitance causes the reduced tolerance for the FD dark current at the switching point from a low light signal (S1) to a bright light signal (S2). However it is solved by the reduction of the electric field concentrations at the FD in conjunction with the LOFIC capacitance optimization. A 1/4 in. video graphics array (VGA) format CMOS image sensor fabricated through 0.18 µm two-poly three-metal process demonstrates both 2.2 e- rms noise floor and an invisible signal-to-noise (S/N) ratio degradation at the S1/S2 switching point under 2 s integration time while the full well capacity is extended up to 100 ke-.

A 200-$\mu$V/e$^{-}$ CMOS Image Sensor With 100-ke$^{-}$ Full Well Capacity

A high-sensitivity CMOS image sensor keeping a high full-well capacity has been developed by introducing a new pixel having a small floating diffusion (FD) capacitance connected to a lateral overflow integration capacitor (LOFIC) through a MOS switch. The conceptual advantage of the small FD approach over conventional column amplifier approaches is compared and demonstrated. To ensure both the high sensitivity and the high full-well capacity, the low-light and the bright-light signals (S1 and S2) are output and reproduced without a visible SNR degradation at the S1/S2 switching point. As the most critical problem, the increase of the conversion gain variation in this approach is suppressed by applying a self-aligned offset structure to the small FD. A 1/4-in VGA format CMOS image sensor fabricated through 0.18-mum 2P3M process achieves 2.2-e- rms noise floor with 200-muV/e- conversion gain and 100-ke- full-well capacity.

A Wide Dynamic Range Photogate-Type Active Pixel Sensor Using a Self-Regulation Principle

A wide dynamic range photogate-type active pixel image sensor based on a self-regulation principle is reported. A 5 ×5 element prototype sensor was fabricated using a 5 µm single-poly, single-metal negative channel metal oxide semiconductor (NMOS) silicon integrated circuit technology. The key techniques are based on the feedback of a floating diffusion (FD) potential to the photogate applied voltage and on the control of the sub-threshold characteristic of the photogate using an ion implantation process. The proposed sensor makes it possible to automatically adjust the sensitivity of each pixel using only three transistors. The conversion of the irradiated light to the output voltage is linear under low-light conditions, while it is nonlinear under bright light. The photo-electric conversion characteristics are similar to those of a linear-logarithmic image sensor. The dynamic range can be expanded without the need for an additional capacitor, an analog-to-digital (A/D) converter or any complex circuitry. Compared with a conventional photogate-type image sensor that was fabricated on the same chip, the dynamic range was expanded by 28 dB.

CMOS image sensors comprised of floating diffusion driving pixels with buried photodiode

New CMOS image sensors that can realize high quality dark scene images with pixels smaller than conventional pixel types are described. The new technologies used to develop them are floating diffusion (FD) driving pixel with a buried photodiode with three or less transistors, and low-voltage driving technologies with a new photodiode structure and FD-boost method. Through the use of the 0.25-/spl mu/m technology, prototype chips consisting of 3.45-/spl mu/m size pixels were manufactured. Prototype chips consisting of 3.1-/spl mu/m size pixels which share FD between two neighboring pixels (2-pixel-sharing) were also manufactured. The complete transfer operation, that is to say, zero lag and zero pixel kTC noise was achieved at a supply voltage of 2.5 V with manufacturing stability. Realized saturation voltages were 510 and 360 mV for 3.45-/spl mu/m and 3.1-/spl mu/m size pixel chips, respectively. In addition, a combined double-correlated double sampling (CDS) architecture which can flexibly process two sets of signals in combination were employed. Due to its small pixel size, high image quality, and output flexibility, this framework has potential for replacing charge-coupled device (CCD) image sensors with CMOS image sensors in volume markets of digital still cameras and camcorders.

The Analysis of Dark Signals in the CMOS APS Imagers From the Characterization of Test Structures

The characteristics of dark signals have been investigated in the CMOS active pixel sensor (APS) with test structures fabricated using the deep-submicron CMOS technology. It is found that the periphery of the photodiode (PD) is the dominant source of dark currents in our test structure, and this factor is very sensitive to the distance between the sidewall of the shallow trench isolation and the n-type region of the PD. The dark currents from the transfer gate can be effectively reduced by the tail of p/sup +/ region on the surface of the transfer gate, and those from the floating diffusion (FD) node were estimated to be negligible in the normal operational mode. However, because of the enhanced thermal generation velocity caused by the severe process-induced damages, the FD node was considered as the main source of increased dark currents in the single frame capture mode. The characteristics of quantized dark currents causing the white pixels in the CMOS APS were examined using the dark current spectroscopy method. Three distinct deep-level bulk traps have been identified with the location in the silicon bandgap at |E/sub t/-E/sub i/|/spl sim/0.020 (eV), |E/sub t/-E/sub i/|/spl sim/0.082 (eV), and |E/sub t/-E/sub i/|/spl sim/0.058 (eV), and capture cross sections of 7.80/spl times/10/sup -15/ cm/sup 2/, 1.83/spl times/10/sup -13/ cm/sup 2/, and 1.46/spl times/10/sup -13/ cm/sup 2/ respectively.

Low-noise and high-speed charge detection in high-resolution CCD image sensors

This paper analyzes problems associated with low-noise and high-speed charge detection encountered in high-resolution image sensors. It is found that the conventional Floating Diffusion (FD) charge detection concept is inferior to the previously studied, but not frequently utilized, Floating Gate (FG) approach. A new output charge detection well reset technique and an improved biasing method allowed the design of the FG charge detection amplifier with a comparable conversion gain to FD structures but with much better noise performance at the data rates up to 40 MHz. The theoretical analysis of the FG amplifier performance, including the Correlated Pixel Clamp signal processing method, is confirmed by measurements performed on a high-resolution 1000/spl times/1000 pixel Frame Transfer CCD image sensor built using an Advanced Virtual Phase Technology. The described details of the sensor design include: (1) the over all device architecture, (2) the pixel cross section with the cross section of the lateral overflow drain antiblooming structure, (3) the dual serial register with a single output amplifier, and (4) the resistive gate reset structure for the output charge detection well. The developed image sensor does not need the conventional Correlated Double Sampling (CDS) circuit for the signal processing, since the FG detection node is sensing charge nondestructively without generation of kTC noise. The described progress in the FG charge detection approach thus opens up a possibility for future designs of distributed FG amplifiers that can theoretically reach the ultimate low-noise performance at virtually any clocking frequency.