Floating Capacitor Voltage Research Articles

A Capacitor Voltage Balancing Scheme for Single-Source Fed Switch Optimized Three-Phase Nine-Level Inverter

This article proposes a novel floating capacitor (FC) and dc-link capacitor voltage balancing scheme for a single-source three-phase nine-level inverter with reduced part count. Although nine levels are generated by keeping the dc-link capacitor voltage to FC voltage ratio as 3:1, it comes with complete absence of any useful pole voltage redundancies. Therefore, the conventionally adopted redundant-state-switching-based pulsewidth modulation technique cannot be applied for FC voltage balancing. Hence, a novel carrier-based modulation scheme is proposed here, which addresses the issue of FC voltage balancing by safely clamping the modulating reference to pole voltage levels that aid in FC voltage balancing. The dc-link capacitor voltages are also balanced using a unique way suitable for this inverter having nonredundant characteristics. Simulation and experimental results verify the capability of the proposed balancing scheme for the optimized nine-level inverter under different modulation and load conditions. It is found that a maximum fundamental phase peak voltage of 0.607 times dc-link voltage (at 0.91 modulation index) can be achieved at unity power factor and, thus, utilizing the dc bus of the inverter effectively.

Decoupled Floating Capacitor Voltage Control of a Dual Inverter Drive for an Open-Ended Winding Induction Motor

A control scheme is presented for a dual inverter drive with a floating capacitor bridge, with decoupled motor and capacitor dynamics. A stator current reference frame is used that decouples the real and reactive power components of the motor and enables the decoupling of the motor and capacitor dynamics. Apart from the high frequency voltage ripple due to the inverter switching pattern, the capacitor voltage can be kept constant even during large step changes in motor speed reference and load torque. This allows for the use of a significantly smaller floating bridge capacitor whose size depends only on the steady-state high frequency voltage ripple. Additionally, the number of PI regulators used compared to previous works and the dc-link voltage requirements are both reduced.

High Gain Active Neutral Point Clamped Seven-Level Self-Voltage Balancing Inverter

This brief presents a novel seven-level (7L) inverter topology for grid-connected renewable applications. It consists of ten active switches and one inner flying-capacitor unit forming a structure similar to conventional active neutral point clamped inverter. The proposed unique arrangement reduces the number of active, passive components and it does not require any sensor to balance the floating capacitor voltage, thereby reduces cost and complexity in the control system design. In addition, compared to major conventional 7L inverter topologies, the proposed topology is capable of boosting the input voltage by a factor of 1.5, thereby, eliminating the need for an intermediate boosting stage. In other words, it reduces the dc-link voltage requirement by 50%. To prove the advantage of the proposed topology over other recent topologies, a comparative study in terms of power components and cost is presented. The operation and performance of the proposed topology for various loading conditions are validated through experimental tests and measurements.

A Neutral Point Voltage Balancing Scheme With Improved Transient Performance for 5-Level ANPC and TNPC Inverters

In this paper, a neutral point (NP) voltage balancing scheme suitable for three phase 5-level active NP clamped and T-type NP clamped (TNPC) inverters is discussed. Carrier-based pulsewidth modulation is used for the balancing of dc-link capacitors and floating capacitors (FC) in the inverter. The FC voltages are regulated with the help of redundant switching states of pole voltage levels and the dc-link capacitor voltages are controlled using zero-sequence voltage injection. Though the balancing approaches are different for dc-link capacitors and FCs, they are not decoupled from each other. This is due to the effect of certain redundant switching states used for FC balancing causing NP voltage variation. To address this issue, the redundant state time ratio is estimated online every sample and based on this dynamic time ratio, an optimal relationship between neutral current and zero-sequence voltage is established. It is found that the use of dynamic time ratio helps in achieving better transient performance than that of generally adopted fixed time ratio. Simulation and experimental results prove that the proposed balancing scheme works well under all operating conditions and exhibits fast and stable transient performance.

Carrier-based sinusoidal pulse-width modulation techniques for flying capacitor modular multi-level cascaded converter

Carrier-based sinusoidal pulse-width modulation (PWM) techniques, such as phase disposoed PWM(PD-PWM) and phase shifted PWM (PS-PWM), are widely applied to control the modular multilevel cascaded converters (MMCC) having full H-bridge as sub-modules. This paper evaluates these PWM techniques when controlling a variant of the H-bridge MMCC, i.e. the MMCC five-level flying capacitor converter as sub-modules. This MMCC poses an extra challenge to PWM schemes; namely maintaining two inner floating capacitor voltage balancing. Two novel PWM techniques known as the swapped carrier PWM techniques are introduced for the control of this converter. The paper compares them with the two conventional ones using a performance metrics composed of voltage waveform performance, capability in natural flying capacitor voltage balancing, converter power loss, and switch utilisation. The results show that the proposed new PWM schemes outperform both conventional methods in both switching and conduction power losses and achieve similar performance like the PS-PWM under the three other metrics.

A New Control Technique for Improved Active-Neutral-Point-Clamped (I-ANPC) Multilevel Converters Using Logic-Equations Approach

The per-phase leg of an improved active-neutral-point-clamped (I-ANPC) multilevel converter is realized by the cascaded connection of the standard ANPC topology and the concatenated H-bridge modules consisting of the flying-capacitors (FCs). This article proposes an innovative approach for the active control of the I-ANPC inverters. The introduced methodology is developed on the basis of the logic-equations set for the active voltage balancing of the FCs within the H-bridge modules, and controlling the generated output voltage. It derives logic-variables employing the direction of the output current, and the deviation of the FCs’ voltages from their target operating levels in the H-bridge cells. These logic-variables are fed into a set of logic-equations derived for the control of the I-ANPC inverter. The regulation of the floating-capacitor voltages at their reference values along with synthesizing the required pulsewidth modulation voltage-level at the output having fast dynamics are the control objectives to achieve. The derived logic-equations and the proposed control method are explored and verified by the experimentally measured results obtained from the 5-kW prototype of a five-level converter.

Enhanced Floating Capacitor Voltage Balancing Schemes for Single-Source Seven-Level Inverters With Capacitor Fed H-Bridge Units

Two novel floating capacitor voltage balancing schemes are proposed in this article, which enhance the linear modulation range of single-source seven-level inverters having floating capacitor fed H-bridge units. Extreme pole voltage levels associated with cascaded H-bridge units can be used for enhancing dc bus utilization. But, these pole voltage levels lack redundant switching states, which limits the linear modulation range for which floating capacitor voltages remain balanced. In recent times, a few literature have addressed the issue of balancing these capacitor voltages by employing appropriate modulation schemes, which enhances the modulation range of a inverter to a certain extent. The proposed balancing schemes further extend the linear modulation range by adding a suitable common-mode offset to reference signals. The addition of a predefined low-frequency offset and an online calculated dynamic offset is proposed here that helps in extending the modulation ranges to 0.84 and 0.85. Under these schemes, the dc bus utilization can reach up to 0.637 V dc at unity power factor, where V dc is the input voltage of the single-source inverters. Three well-established optimized seven-level inverters are used to analyze these schemes and their effectiveness is demonstrated using simulation and experimental results at different modulation and load conditions.

An Active Modulation Scheme to Boost Voltage Utilization of the Dual Converter With a Floating Bridge

This paper proposes a capacitor voltage regulation method for the dual converter with a floating bridge for aerospace applications. This topology has previously been reported, but with a constrained voltage utilization factor due to the need for capacitor voltage regulations. In this paper, the effect of switching states on the voltage variation of capacitor is quantitatively modeled and an enhanced space vector modulation scheme with current feedback is proposed to achieve an active control of the floating capacitor voltages. This proposed method also allows further exploitation and utilization of converter voltage. The relationship between the allowed modulation index of dual converter and load power factor is obtained and expressed using a fitted polynomial equation. The advantages of the proposed method include boosted voltage utilization and superior performance in term of capacitor voltage balance. These advantages have been proven through simulation and experimental results on RL loads as well as with an open-end winding induction motor. The proposed modulation scheme can boost the converter voltage utilization by at least 10% while achieving full four-level operation. More importantly, the higher available voltage allows extending the constant torque region of the motor, the further beginning of field weakening operation could be postponed.

An Improved Seven-Level PUC Inverter Topology With Voltage Boosting

In this brief, a seven-level (7L) improved packed U-cell (IPUC) inverter with reduced power electronic components is proposed. The presented IPUC inverter has low voltage stress on switches and is capable of voltage boosting. A new voltage balancing method based on logic form equations is developed for regulating the inherent floating capacitor voltage to half the input dc voltage. The proposed 7L IPUC is compared with other state-of-the-art 7L inverters in terms of number of IGBTs, blocking voltage, and driver circuits for attesting its superior merits. The performance of the proposed voltage balancing is verified through a laboratory prototyped 7L IPUC inverter considering varying load conditions and the corresponding results are elucidated.

Investigation on Extending the DC Bus Utilization of a Single-Source Five-Level Inverter With Single Capacitor-Fed H-Bridge Per Phase

Enhancement of dc bus voltage utilization for a five-level inverter with single dc source and capacitor-fed H-bridge (CHB) units is investigated in this paper. A carrier-based modulation technique is used for boosting the dc bus utilization, which is established by providing detailed mathematical analysis. The five-level inverter used here is realized by cascading a CHB unit to each phase of a three-level neutral point clamped inverter. The increase in dc bus voltage utilization owes to the pole voltage redundancies offered by CHB units. The floating capacitors of H-bridge units are balanced within a quarter fundamental cycle using the switching state redundancies of pole voltage levels. The aforementioned modulation technique allows the inverter to enhance the dc bus utilization from 0.577 $\text{V}_{\text{dc}}$ to 0.63 $\text{V}_{\text{dc}}$ under unity power factor. This enhancement is obtained in the linear modulation range without increasing the dc bus voltage, and thus, the inverter can operate without the presence of low-order harmonics in its phase voltages. The strength of this paper lies in its detailed mathematical analysis for finding out the limiting modulation index and power factor condition in the light of floating capacitor voltage balancing issue. Simulation as well as experimental verification of the modulation scheme is carried out on an induction motor drive under various operating conditions. It is shown that this carrier-based modulation technique is suitable for any single source inverter topology with one CHB unit per phase.

Active Capacitor Voltage-Balancing Methods Based on the Dynamic Model for a Five-Level Nested Neutral-Point Piloted Converter

This paper presents the active capacitor voltage-balancing (ACVB) methods based on the dynamic model for a five-level nested neutral-point piloted (NNPP) converter using hybrid carrier modulation. The traditional hybrid carrier modulation provides natural voltage balancing of floating capacitors and dc-link capacitors. First, the natural voltage-balancing ability under steady-state and ideal conditions is theoretically proved. However, there are accumulated errors and deviations of capacitor voltages in practical applications, especially under dynamic conditions. In order to address the accumulated errors and deviations of capacitor voltages, the dynamic models of floating-capacitor voltages and neutral-point voltage are established. Moreover, the ACVB method based on the dynamic model of the neutral-point voltage is proposed by injecting the zero-sequence voltage. And the ACVB method based on the dynamic model of floating-capacitor voltages is proposed by introducing the adjustment variables. The proposed ACVB methods have the advantages of simple formula, definite physical meaning, and high accuracy. Furthermore, the output voltage quality and current quality are evaluated in term of total harmonic distortion and the effect of model parameter mismatch on the proposed ACVB methods is presented. Finally, the comparative simulation and experimental results verify the correctness of the proposed ACVB methods based on the dynamic model under different conditions.

A Novel Seven-Level Hybrid-Clamped (HC) Topology for Medium-Voltage Motor Drives

This letter proposes a novel seven-level (7L) hybrid-clamped converter, which has competitive performance and lower device count compared to existing topologies. It can easily balance the floating capacitor voltage at the switching frequency, and therefore ensure low capacitor voltage ripples even under very low fundamental frequencies. Both multipulse diode front-end and active front-end structures can be used with the proposed 7L converter, where the 7L active front end has the ability to balance the dc-link capacitors. The proposed 7L converter is very suitable for medium voltage drives (4.16 to 6.6 kV) that feature low costs, high-performance, and low-speed operation capability. Simulation and experiment results are obtained to verify the feasibility of the proposed topology.

Carrier-Based Stair Edge PWM (SEPWM) for Capacitor Balancing in Multilevel Converters With Floating Capacitors

Multilevel converters with floating capacitors (FCs) are widely applied in recent years in a wide range of industrial applications from high-voltage direct current systems to high power drives. However, some FC topologies lack complete FC voltage balancing capability due to the inherent topology limitation or the insufficient switching state for capacitor balancing. This will result in large ripples on capacitors at low frequency (such as fundamental frequency), limiting their performance and application, particularly, when the fundamental frequency is very low in low-speed drive operations. Typical examples of those multilevel converters are modular multilevel converters (MMC), nested neutral-point-clamped (NNPC) converter, etc. In order to improve the FC balancing for this kind of multilevel converters, this paper proposes a carrier-based pulse-width modulation (PWM) method, named stair edge PWM method. This method can obtain sufficient redundant switching states for FC voltage balancing by producing multiple levels in one PWM period. The FC voltage balancing is thus achieved at switching frequency, which can greatly reduce the capacitor voltage ripple and therefore enable the use of much smaller FCs. Meanwhile, the voltage stress on each device and low $dv/dt$ feature are still the same as the normal multilevel operation, reserving two of the most salient features of multilevel converters. The proposed method also features much simpler and easier implementation compared with space-vector-based approaches, particularly when high-level converters are considered. An application example using a four-level NNPC converter is provided in this paper. The effectiveness and performance of the proposed method are verified by both simulation and experiment.

A Switched-Capacitor-Based Multilevel Inverter Topology With Reduced Components

This letter presents an improved sensorless nine-level inverter topology with reduced number of components. It is formed by cascading a three-level T-type neutral clamped point inverter with a floating capacitor (FC) fed two-level converter unit. Additionally, two line-frequency switches are appended across the dc-link. A simple logic-form equations-based pulse width modulator is designed which is in-charge of maintaining the FC voltage at its reference value without any aid of voltage and current sensor. Thus, the complexity in control of the proposed topology is very minimal. The working principle of the proposed inverter and formulation of logic-form equations is deliberated in detail. Furthermore, experimental results obtained from the developed prototype are presented to validate feasibility and operability of the proposed topology. Finally, a comprehensive comparison with some of the recently reported inverter topologies proving the merits of the proposed topology is included.

Modeling, control, and reduced-order representation of modular multilevel converters

This paper presents a reduced-order model of the modular multilevel converter (MMC) for electromechanical transient simulations and small-signal analysis. The MMC model is firstly developed in detail; then, simplifications are introduced to reduce it to eleventh- and fourth-order models. The dynamic behaviors of the traditional voltage-source converter and the MMC are also compared. A thorough description of the MMC control system is presented including the inner current control loops, the outer voltage control loops, and the strategy to balance the floating capacitor voltages. Control systems in continuous- and discrete-time domains are given to enable their use in power system simulations and in practical implementations, respectively. Several tests are performed to compare the steady-state and transient response of the detailed and the reduced models. The results show that the fourth-order reduced model can properly capture the input-output dynamics of a complete MMC and significantly reduce the computational cost of large-scale power system simulations with multiple ac/dc converter stations.

Three-Phase Unidirectional Rectifiers With Open-End Source and Cascaded Floating Capacitor H-Bridges

This paper presents two topologies of three-phase semicontrolled rectifiers suitable for open-end ac power sources. The rectifiers are composed of a combination of two-level three-phase bridges (controlled, semicontrolled, or uncontrolled) and three single-phase floating capacitor h-bridges (controlled). These topologies generate two powered dc-links, each one belonging to a three-phase bridge. They present a reduced number of controlled power switches if compared with other open-end configurations of similar complexity found in the literature. It is also proposed a space-vector pulse-width modulation (SV-PWM) approach and a method of floating capacitor voltage control dedicated to the topologies with an equivalent approach based on the level-shifted PWM (LS-PWM). The proposed SV-PWM solving method is based on a redundant state selection (RSS) technique, which allows the floating capacitors voltage regulation. On the other hand, the LS-PWM solving method is based on the neutral voltage selection, which is shown to be equivalent to the SV-PWM RSS technique seen from the control system. Simulation results are shown to validate proposed topologies, as well as the SV-PWM and LS-PWM techniques, and the control strategy. Experimental results are shown to demonstrate proposed configurations feasibility.

Hybrid Seven-Level Converter Based on T-Type Converter and H-Bridge Cascaded Under SPWM and SVM

This paper presents a hybrid seven-level converter based on T-type converter and H-bridge cascaded suitable for low-voltage and high-power-density applications. The operation principles and conduction paths are analyzed comprehensively. Voltage balance control of the floating capacitors is the key point of this paper. Mathematical expressions of capacitor voltage balance conditions are deduced based on sinusoidal pulse width modulation (SPWM). The results show that floating capacitor voltages are only balanced when the modulation index is below 0.82 under SPWM. In order to enlarge the modulation index ensuring the capacitor voltage balance, space vector modulation (SVM) is also applied to regulate floating capacitor voltages taking advantage of redundant switching vectors. Meanwhile, in SVM, there are no additional control requirements for the capacitor voltage. Taken both SPWM and SVM into consideration, the limit to the range of operation for this seven-level converter is presented, which is a function of the modulation index and the power factor. The merit of dc voltage utilization improvement in this topology is also analyzed based on simulation results. Simulations and experimental results under different modulation index and RL load are presented to verify the modulation strategies illustrated in this paper.

Operation and Control of an Improved Hybrid Nine-Level Inverter

This paper proposes a new nine-level inverter for medium- and high-power applications. The proposed topology comprises of a three-level (3L) active neutral-point-clamped (ANPC) inverter connected in series with a floating capacitor (FC) fed H-bridge. Besides, two additional switches operating at line frequency are appended across the dc link of the 3L ANPC structure. Compared with conventional hybrid cascaded inverters, the primary advantage of this addition is doubling of the resulting root mean square output voltage. This amelioration is achieved while preserving the standard 3L ANPC and H-bridge structures with minimum topological modification. A simple logic-gate-based voltage balancing scheme is developed to regulate the FC voltage. The proposed voltage balancing method is independent of load power factor, inverter modulation index, and can balance the voltage across FC instantaneously. The step-by-step formulation of logical expressions for the generation of gating pulses is deliberated in detail and can be generalized for any $n$ -level inverter. Further, simulation results as well as the experimental measurements obtained from the laboratory prototype are presented to validate the effectiveness and practicability of the proposed configuration. Finally, the notable merits of the proposed inverter over the prior art topologies is established through a comprehensive comparative study.

Design and Implementation of a Sensorless Multilevel Inverter With Reduced Part Count

This letter proposes a single-phase nine-level (9L) inverter topology suitable for grid-connected renewable energy systems. The proposed inverter is realized using a T-type neutral-point-clamped inverter connected in cascade to a floating capacitor (FC) H-bridge. Additionally, two low-frequency switches are added across the dc-link enabling the inverter to generate a 9L waveform. A sensorless voltage control based on redundant switching state is developed and embedded with PWM controller, which is responsible for regulating the FC voltage at one-quarter of the dc source voltage. The proposed PWM technique employs the generation of 9L waveform without using any voltage sensor, thereby reducing the complexity of the overall control scheme. This, in turn, will make the overall system appealing for various industrial applications. In comparison to conventional and recent topologies, generation of the 9L waveform using a lower number of components is the notable contribution. Another important feature of the proposed inverter is that if FC H-bridge fails, it can be bypassed, and the inverter can still operate as a 5L inverter at its nominal power rating. Furthermore, a comprehensive comparison study is included which confirms the merits of the proposed inverter against those of other state-of-the-art topologies. Finally, simulation and experimental results are included for validating the feasibility of the proposed system.

A Space Vector Pulse Width Modulation for Five-Level Nested Neutral Point Piloted Converter

This paper introduces a novel five-level nested neutral point piloted (NNPP) converter and analyzes the operating principle of five-level NNPP converter. This paper presents a novel space vector pulse width modulation (SVPWM) algorithm based on gh coordinate for five-level NNPP converter. First, the common-mode voltage is reduced by choosing the appropriate redundant switching states. After that, the floating-capacitor voltage balance control strategy is presented. The appropriate switch combinations of each phase are determined by the control requirements of floating-capacitor voltages respectively and the hardware mapping method of the switching states is presented. Furthermore, the neutral-point voltage balance control strategy is presented. In order to balance the dc-link capacitor voltages, the seven-segment switching sequence is selected according to the control requirements of dc-link capacitor voltages and the neutral-point voltage regulatory factor is introduced to regulate the durations of the redundant switching states in a switching cycle. Finally, the validity of the novel SVPWM algorithm with decoupling control strategies of floating-capacitor voltages and dc-link capacitor voltages is verified by the experimental results of five-level NNPP converter under steady-state and dynamic conditions.