Flipped Voltage Follower Cell Research Articles

Implementation of a Double-Path Flipped Voltage Follower Cell for Voltage Conveyors

Implementation of a Double-Path Flipped Voltage Follower Cell for Voltage Conveyors

A 4.65 [formula omitted]V/V line regulation, transient enhanced, capacitor-less LDO with ultra-low load current dependence

A capacitor-less low-dropout regulator (CL-LDO) based on an improved flipped voltage follower (FVF) cell with robust regulation capability and high transient response is presented. The line regulation (LNR) and load regulation (LAR) are enhanced by a stable DC operating point design and multiple feedback loops. A nested feed-forward gm-stage and a nulling resistor in the nested Miller compensation (NGRNMC) topology ensures stability in various challenging conditions. The proposed CL-LDO was designed in 0.18μm BiCMOS technology and occupied an area of 0.0582 mm2, with a typical input voltage range of 3.0 V–3.6 V and a load range of 0–100 mA. Post-simulation verification under various process, voltage, and temperature (PVT) conditions confirms the design’s robustness and reliability. The proposed design achieves the best figure of merit (FoM) of 1.69 mV among state-of-the-art designs, accompanied by a LNR of 4.65 μV/V and a LAR of 27.881 nV/mA.

A wide-swing class-AB level-shifted bulk-driven folded flipped voltage follower cell with the low output resistance

A wide-swing class-AB level-shifted bulk-driven folded flipped voltage follower cell with the low output resistance

A push-pull FVF based LDO voltage regulator with slew rate enhancement at the gate of power transistor

A low-dropout (LDO) voltage regulator based on a push-pull flipped voltage follower cell with slew rate improvement at the gate of power transistor is presented. The proposed three-stage regulator exploits two separate signal paths by cross-coupled common-gate cells to improve the transient response and loop stability with low power consumption. Moreover, a slew rate enhancement technique is employed at the gate of power transistor by adding a new current signal path which also improves the small-signal behavior. It is simulated in Cadence with a 90 nm CMOS process, 2.1 μW minimum power dissipation, and 150 mV dropout voltage for 0.9–1.2 V input voltage. It is stable over a range of 40 μA–100 mA load currents and 100 pF load capacitor. The achieved settling time is about 1.2 μs when the load current changes from 40 μA to 100 mA with 200 ns rise time. The obtained line and load regulations are 0.4 mV/V and 6 μV/mA, respectively.

A high output resistance, wide bandwidth, and low input resistance current mirror using flipped voltage follower cell

AbstractThe paper proposes a current mirror designed using the current sensor structure of class‐AB flipped voltage follower cell at the input stage and super cascode structure at the output stage. The proposed current mirror offers low input resistance due to the current sensor at the input stage and high output resistance due to super cascode configuration at the output stage. The proposed current mirror offers a good dynamic range of 0 to 300 μA with less copying error of 0.54%, wide bandwidth of 319.8 MHz, high output resistance of 19.8 GΩ, and low input resistance of 161.34 Ω. The proposed current mirror is designed using BSIM3V3 180‐nm CMOS technology and simulated using spectre in the Cadence Virtuoso analog design environment at room temperature. The Cadence Virtuoso layout XL editor has been used to design the physical layout of the proposed current mirror. The pre‐layout and post‐layout simulation results of the proposed current mirror have been shown to validate its performance. The Monte Carlo analysis has also been performed to analyze the effects of process variations and mismatches on the performance of the proposed current mirror.

A very low output resistance and wide-swing class-AB level-shifted folded flipped voltage follower cell

The paper presents a class-AB flipped voltage follower (FVF) cell. In contrast to previous works in the literature, FVF cell, level shifter and folded FVF cell are merged in the proposed FVF cell to offer class-AB operation along with wide input/output voltage swing and low output resistance. In the proposed FVF cell, the level shifter increases the input/output voltage swing while the folding transistor provides an alternate path for sourcing current, which results in low output resistance. The proposed FVF cell offers wide input/output voltage swing of 0.80 V/0.67 V, high gain of 0.84, wide bandwidth of 54 MHz for the worst case load capacitance of 50 pF and low output resistance of 10 Ω. The proposed FVF cell is simulated using Cadence Virtuoso Analog Design Environment in 180 nm CMOS technology. The physical layout has been designed using Cadence Virtuoso Layout XL editor and post-layout simulation results are presented to demonstrate the performance of the proposed FVF cell. The corner analysis has also been performed to show the robustness of the proposed FVF cell.

A four quadrant high-speed CMOS analog multiplier based on the flipped voltage follower cell

In this work the design and implementation of a High-Speed Four-Quadrant CMOS Analog multiplier is presented. The proposed multiplier uses the Gilbert cell as the main core. However, instead of processing both input and output signals in voltage or current mode, the “x” input signal is applied in voltage mode while the “y” input signal and “o” output signal are processed in current-mode. This approach is achieved by means of using very-low-impedance nodes at the “y” and “o” ports which also helps to enhance the overall bandwidth of the proposed multiplier. Both very-low-impedance nodes are implemented using the Flipped Voltage Follower (FVF) as high-speed high-performance low-voltage current mirror. The implemented circuit shows a bandwidth of 260 MHz for a 50Ω‖30pF load, presents a 1.5% THD at 100 MHz, and consumes 7.5 mV using a ±1 V symmetric power supply. In order to validate theory and simulations, a prototype of the multiplier was fabricated and tested using a 0.5 μm CMOS standard fabrication process; a silicon area consumption of 520 μm × 70 μm was observed. Measurements shows that the proposed multiplier is suitable for its implementation in the low corner of the Very High Frequency (VHF) band.

Class-AB Flipped Voltage Follower Cell with High Current Driving Capability and Low Output Resistance for High Frequency Applications

In this paper, a class-AB flipped voltage follower cell with high current driving capability is proposed. The proposed flipped voltage follower (FVF) cell offers increased current sourcing capability and large input/output voltage swing due to the use of bulk-driven and level shifter techniques, respectively. Further, it uses an additional NMOS transistor connected between output and ground terminals to increase the current sinking capability and to reduce the output resistance. The stability analysis has been performed by using Routh–Hurwitz stability criteria which confirms that the proposed FVF cell is stable. The proposed FVF cell also offers a high symmetrical slew rate. The proposed FVF cell has been simulated in Cadence virtuoso analog design environment using BSIM3v3 180 nm CMOS technology and simulation results are presented to validate the effectiveness of the proposed circuit.

A Low-Power High-Gain Low-Dropout Regulator for Implantable Biomedical Applications

This paper presents an ultra-low-power and high-gain low-dropout (LDO) regulator. It is based on the flipped voltage follower cell with an adaptive biasing technique that is suitable for implantable biomedical applications. The error amplifier for the proposed regulator consists of two cross-coupled common-gate cells and a pseudo-folded-cascode structure to increase the regulator’s loop gain. In addition, three different compensation techniques including Miller, cascode, and Q-reduction are simultaneously utilized at the LDO regulator to achieve high stability despite having the minimum load current and ultra-low power consumption. The proposed LDO regulator has been simulated in TSMC 90-nm CMOS technology with minimum power consumption of 2.8 µW at no load. Post-layout simulation results show that the proposed LDO regulator is stable over load currents from 30 µA to 40 mA with a maximum on-chip CL of 100 pF. Moreover, the voltage regulator settles in less than 850 ns at 0.75 V output voltage that is achieved in response to a load transient step of 40 mA with a rise time of 200 ns. Besides, the obtained line and load regulations are significantly improved to 1 mV/V and 36 µV/mA, respectively.

High slew rate and low output resistance class-AB flipped voltage follower cell with increased current driving capability

High slew rate and low output resistance class-AB flipped voltage follower cell with increased current driving capability

A class‐AB flipped voltage follower cell with high symmetrical slew rate and high current sourcing/sinking capability

SummaryThe paper presents a class‐AB flipped voltage follower (FVF) cell based on quasi‐floating gate and bulk‐driven techniques. The quasi‐floating gate technique is used to increase the current sinking capability, whereas the bulk‐driven technique is used to enhance the current sourcing capability by reducing the threshold voltage. Using these two techniques, the proposed class‐ AB FVF cell offers high current sinking and sourcing capabilities. Also, it provides high symmetrical slew rate without any additional circuitry. The physical layout of the proposed class‐ AB FVF cell has been designed in Cadence Virtuoso Layout XL editor using BSIM3v3 180‐nm CMOS technology, and post‐layout simulation results have been presented to validate its performance. The corner analysis of the proposed class‐ AB FVF cell has also been performed with temperature and supply voltage as design variables to show its performance under extreme conditions.

Low-Voltage Flipped Voltage Follower Cell Based Current Mirrors for High Frequency Applications

The paper proposes low-voltage current mirrors namely low-voltage current mirror (LVCM) and flipped voltage follower based low-voltage current mirror (FVFLVCM) with high bandwidth. The stability of the proposed circuits has been performed by time-domain approach and frequency domain approach using Routh–Hurwitz stability criteria and phase margin calculations, respectively. The bandwidth of the proposed FVFLVCM has also been enhanced using resistive compensation technique. The proposed LVCM and FVFLVCM have wide input current range of 0–100 µA and 0–150 µA, low DC error of 5.9% and 4.9%, low DC power dissipation of 110.39 µW and 99 µW, high bandwidth of 367 MHz and 624 MHz, low input impedance of 16.3 KΩ and 12.3 KΩ, low THD of 0.26% and 1% and low output noise of 2.25 nA and 2.83 nA over 100 MHz, respectively. The results have been simulated using SPICE in the TSMC 0.18 µm CMOS technology and are presented to validate the effectiveness of the proposed current mirrors.

High Performance CMOS Current Mirror Using Class-AB Level Shifted Bulk Driven Flipped Voltage Follower Cell

This paper presents a novel current mirror structure based on level shifted class-AB flipped voltage follower cell, which operates at the supply voltage of 1.2[Formula: see text]V. The level shifted class-AB flipped voltage follower cell and regulated cascode structure are used at the input and the output stages to achieve low input resistance and very high output resistance, respectively. A comparison of performance parameters of the proposed current mirror with existing structures shows that the proposed current mirror has a very less current tracking error of 0.99%, high output resistance of 18.7[Formula: see text]M[Formula: see text], wide bandwidth of 239.245[Formula: see text]MHz and low power dissipation of 104[Formula: see text][Formula: see text]W. The proposed circuit has been simulated in Cadence virtuoso analog design environment and layout of the proposed circuit has been designed in Cadence virtuoso layout XL editor using BSIM3V3 180[Formula: see text]nm CMOS technology. The post-layout simulation results have also been presented to demonstrate the effectiveness of the proposed circuit.

Class‐AB level shifted flipped voltage follower cell using bulk‐driven technique

In this study, a novel level shifted version of flipped voltage follower (FVF) cell, which provides efficient class-AB operation, is presented. The level shifter is used to increase the swing of the FVF cell. In the proposed circuit, a bulk-driven metal-oxide-semiconductor field effect transistor is used as a current source to improve the sourcing capability and symmetrical slew rate for the class-AB operation. The circuit has a high-input/-output swing of 1.01 V/0.80 V, wide bandwidth of 751 MHz and low-output resistance of 107 Ω. The proposed circuit has been designed and simulated in a Cadence Virtuoso Analog Design Environment using BSIM3v3 180 nm complementary metal-oxide-semiconductor technology. The post-layout simulation results have also been presented to demonstrate the performance of the proposed circuit.

Indirect frequency compensation technique using flipped voltage follower cell

ABSTRACTIn this paper, a useful frequency compensation technique for a three-stage fully differential amplifier with a recycling folded cascode (RFC) input stage structure is presented. The proposed compensation technique is based on using flipped voltage follower (FVF) cell in the RFC structure. This approach merges improved cascode and indirect compensation techniques that the output node of the FVF cell is used for the second one. The proposed circuit yields a higher gain bandwidth (GBW) than the other indirect compensation techniques at the cost of a more complex design procedure. This idea is simulated using 0.18 µm CMOS technology. Simulation results show a 125 dB DC gain, a 41 V/µs slew rate, a 44 MHz GBW, and a phase margin of 76°. The amplifier consumes 695 µW while driving a 30-pF load.

A three-stage class AB operational amplifier with enhanced slew rate for switched-capacitor circuits

In this paper, a three-stage class AB operational transconductance amplifier (OTA) with large slew rate is presented. The reversed nested Miller compensation technique is used to stabilize the proposed OTA, allowing the slew rate enhancement to be achieved by using class AB input and output stages. A flipped-voltage follower cell in the first stage in combination with a switched-capacitor level shifter in the last stage are utilized to implement the class AB operation. Circuit level simulation results are provided using HSPICE and a 90 nm CMOS technology which show 306 % enhancement in the large-signal FoM with approximately the same power dissipation compared to the class A OTA. The achieved settling time with 0.02 % accuracy for the proposed class AB and conventional class A OTAs are 7.5 and 15.3 ns, respectively.

High frequency flipped voltage follower with improved performance and its application

In this paper a wideband flipped voltage follower (FVF) with low output impedance at high frequency has been proposed. Inductive-peaking-based bandwidth extension technique is employed in the FVF cell. The small signal high-frequency analysis of both conventional and proposed FVF has been done. It is shown in analytical derivation of the proposed FVF that by adding an inductive element in the feedback path, the bandwidth is enhanced. Simulation results show that bandwidth extension ratio (BWER) of proposed FVF is about 2.00, without extra dc power dissipation. A wideband low voltage current mirror has been developed by using proposed FVF in place of conventional FVF and by doing so, BWER of 2.98 has been achieved. The performances of circuits are verified in TSMC 0.18μm CMOS, BSIM3 and Level 49 technology with 1.5V power supply and by using Spectre simulator of Cadence.

A new flipped voltage follower with enhanced bandwidth and low output impedance

The paper proposes a flipped voltage follower (FVF) cell with wider bandwidth and lower output impedance as compared to the conventional FVF. These improvements are obtained by adding a resistance in the feedback path of conventional FVF. A current mirror is implemented by using proposed FVF cell to verify the performance improvement. The circuits are designed in TSMC 0.18-µm CMOS technology with 1.5 V supply voltage. The simulation results show that bandwidth extension ratio (BWER) of newly developed FVF is 1.4 without peaking and 1.7 with peaking. The BWERs of the passive-compensated current mirror implemented by using proposed FVF cell are 1.28 without peaking and 1.58 with peaking in the frequency response.

A tunable highly linear CMOS transconductor with 80 dB of SFDR

This paper presents a new tunable CMOS differential transconductor with an SFDR ranging from 80 to 94 dB. It is based on a core of two voltage buffers with local feedback loops to achieve low-output impedance. The two buffers drive an integrated polysilicon resistor, which is the actual transconductance element. The current generated at the resistor is delivered directly to the output using source coupled pairs. This avoids distortion generated by conventional architectures using current copying cells. The voltage buffers are based on the compact flipped voltage follower (FVF) cell. The proposed transconductor relies on the gain of local feedback loops instead of harmonic cancellation. This leads to a simpler design and less mismatch sensitivity. The proposed transconductor bandwidth is closer to that of the typical open-loop design than to one with global feedback, since the local feedback loop is much faster than a global one. It can be tuned down 20% of its maximum g m which is enough to compensate for process variations. The proposed circuit was fabricated in a 0.5 μm CMOS technology and powered by a 5 V single supply. It was measured with 2 Vpp input signals up to 10 MHz. The maximum g m value is 660 μA/V. The transconductor consumes 30 mW and occupies roughly a die area of 0.17 mm 2. Experimental results are presented to validate the proposed circuit.