Flip Flop Research Articles

VLFF — A very low-power flip-flop with only two clock transistors

Flip-flops (FFs) are an essential component of digital circuits, yet they use a lot of power and energy. This paper introduces the VLFF, an extremely low-power flip-flop that operates with just two single-phase clock transistors. The extracted simulation results show that VLFF is the most power-efficient FF amongst all examined FFs for the data activity (DA) range of 0% to 45%. Test-chip measurement results for the test-chip designed in TSMC CMOS 65 nm gp PDK demonstrate that at VDD = 1 V, power consumption is reduced by 63% and 16% with 12.5% DA, and 52% and 6% with 25% DA in comparison to TGFF and 18TSPC, respectively.

Effects of Urban Lighting at Night on Daytime Songbird Aggression

Many animals require sleep for daily functions. In spring, songbirds expend a great deal of energy early in the day by singing to attract mates and aggressively protecting territory. Some evidence suggests that artificial lighting at night (ALAN) in the environment of wild birds increases their nighttime activity that, in turn, contributes to sleep loss. This study investigated how ALAN affects northern cardinal (Cardinalis cardinalis) response to experimental aggressive intrusion by conspecifics. The hypothesis tested is that high ALAN near cardinal roosting spots would cause those individuals to have less energy for daytime aggressive behaviors. After selecting known dark and bright urban roosting locations, ALAN was measured at specific sites with active cardinal territories during nighttime hours. Observers returned in the morning to present cardinal territorial songs using standardized call playback protocols. Aggressive behaviors of responding cardinals were recorded and used to quantify aggression intensity. Standard aggression measures included response latency, distance from bird to speaker, number of songs, hops, and flip flops. An aggression index was obtained using factor analysis which confirmed that aggressive responses featured short latency and approach distances, few chips, and many songs, flip flops, and hops. Analysis of variance revealed that cardinals roosting in high ALAN engaged in significantly more aggressive morning responses; directly contradicting predictions and previously published findings. One possible explanation for this result is that high ALAN might improve sleep in cardinals. To test this, autonomous recording units (ARUs) were placed in study locations to record nighttime calling behaviors in high and low ALAN. Insufficient data were obtained to clarify whether nighttime activity was reduced significantly by ALAN exposure. However, results showed that nighttime activity by cardinals is strongly influenced by moonlight, and that determination of the influence of ALAN on nighttime and daytime avian behavior must include measures of lunar illumination.

Engineered Gate based Nanoscaled JK Flip Flop: Design, Simulation and Applications

Engineered Gate based Nanoscaled JK Flip Flop: Design, Simulation and Applications

PDQRRFF: Poisson-distributed quantum random reversible flip flop generator for BIST

Reversible logic has gained popularity recently because it allows circuits to use significantly less power. Due to the inherent reversibility of quantum operation, there is enormous interest in designing and optimizing reversible circuits. In this work, a new gate named as transvidkan gate, Quantum Random Reversible Flip Flop, Sequence generator, and Build in Self-Test (BIST) has been proposed. Quantum Random Reversible Flip Flop (QRRFF) is an emerging technology that is used in a variety of apps that use modern security and encryption systems. For creating a random string, typical approaches combine an entropy source with an elimination or bit-generation system. Quantum computing reversible logic chips and Low-power design are emerging as intriguing research topics. A classical logic-based 8-bit reversible comparator is represented using existing reversible gates. This study provides a BIST-based architecture for a comparator design that reduces the garbage outputs, quantum cost, and constant inputs. According to simulation result, the proposed approach outperforms traditional methods in terms of hardware complexity and quantum cost.

An Enhanced LPRAFF with Tri-State Inverter Embedded Non-Clock Gating via the CT-GWO Algorithm

Since a long time ago, it has been understood how radiation affects digital circuits, particularly those using the Complementary Metal Oxide Semiconductor (CMOS) model. Total Ionisation Dose (TID) and Single Event Effects (SEE) are the two most significant radiation effects. Depending on the gate input count, the complexity of the circuit will rise, which will worsen the radiation and raise the cumulative dose levels. The incremental dose level affects the circuit parameter failure, which affects how well the logic design functions. Many authors concentrate on minimising the effects of radiation while preventing function loss, but these extra efforts use excess energy. To improve the efficiency of the Low Power Radiation Aware (LPRA) circuit, this paper introduces optimisation concepts in a Flip Flop (FF) architecture named Chaos Theory-based Grey Wolf Optimised FF (CT-GWOFF). First, compute each component's radiation response using a physics-based modelling strategy. To minimise undesirable latches and disable the inverter chain when the input data remain constant, a tri-state inverter, incorporating a non-clocked gating mechanism, is provided. This prevents repeated transitions of delayed clock signals. Moreover, the proposed model is implemented in FFs for simulation purposes, making it more cognizant of radiation effects and power consumption. Using the HSPICE tool, the performance of the suggested circuit design is evaluated at the 16 nm CMOS Predictive Technology Model (PTM).

An FPGA-Implemented Antinoise Fuzzy Recurrent Neural Network for Motion Planning of Redundant Robot Manipulators.

When a robot completes end-effector tasks, internal error noises always exist. To resist internal error noises of robots, a novel fuzzy recurrent neural network (FRNN) is proposed, designed, and implemented on field-programmable gated array (FPGA). The implementation is pipeline-based, which guarantees the order of overall operations. The data processing is based on across-clock domain, which is beneficial for computing units' acceleration. Compared with traditional gradient-based neural networks (NNs) and zeroing neural networks (ZNNs), the proposed FRNN has faster convergence rate and higher correctness. Practical experiments on a 3 degree-of-freedom (DOs) planar robot manipulator show that the proposed fuzzy RNN coprocessor needs 496 lookup table random access memories (LUTRAMs), 205.5 block random access memories (BRAMs), 41384 lookup tables (LUTs), and 16743 flip-flops (FFs) of the Xilinx XCZU9EG chip.

Design of All-Optical D Flip Flop Memory Unit Based on Photonic Crystal.

This paper proposes a unique configuration for an all-optical D Flip Flop (D-FF) utilizing a quasi-square ring resonator (RR) and T-Splitter, as well as NOT and OR logic gates within a 2-dimensional square lattice photonic crystal (PC) structure. The components realizing the all-optical D-FF comprise of optical waveguides in a 2D square lattice PC of 45 × 23 silicon (Si) rods in a silica (SiO2) substrate. The utilization of these specific materials has facilitated the fabrication process of the design, diverging from alternative approaches that employ an air substrate, a method inherently unattainable in fabrication. The configuration underwent examination and simulation utilizing both plane-wave expansion (PWE) and finite-difference time-domain (FDTD) methodologies. The simulation outcomes demonstrate that the designed waveguides and RR effectively execute the operational principles of the D-FF by guiding light as intended. The suggested configuration holds promise as a logic block within all-optical arithmetic logic units (ALUs) designed for digital computing optical circuits. The design underwent optimization for operation within the C-band spectrum, particularly at 1550 nm. The outcomes reveal a distinct differentiation between logic states '1' and '0', enhancing robust decision-making on the receiver side and minimizing logic errors in the photonic decision circuit. The D-FF displays a contrast ratio (CR) of 4.77 dB, a stabilization time of 0.66 psec, and a footprint of 21 μm × 12 μm.

A demultiplexer-based dual-path switching true random number generator

This paper presents a demultiplexer (DEMUX) based dual-path switching true random number generator (TRNG). Unlike the classical single chain TRNG, the proposed TRNG utilizes DEMUXs to separate the cumulative jitter and occurrence of metastability in two paths. It also uses Ring Oscillator (RO) to increase the uncertainty of path switching time. Therefore, two sources of entropy are skilfully combined and no post-processing circuitry is required. The proposed structure is implemented on Xilinx Virtex-7 FPGA development board. The experimental results show that the proposed structure is able to achieve a high throughput of 500 Mbps with 33 Look-up Tables (LUTs) and 4 Flip-Flops (FFs). This effectively improves the throughput with high quality entropy and low hardware overhead.

Entropy Analysis of FPGA Interconnect and Switch Matrices for Physical Unclonable Functions

Random variations in microelectronic circuit structures represent the source of entropy for physical unclonable functions (PUFs). In this paper, we investigate delay variations that occur through the routing network and switch matrices of a field-programmable gate array (FPGA). The delay variations are isolated from other components of the programmable logic, e.g., look-up tables (LUTs), flip-flops (FFs), etc., using a feature of Xilinx FPGAs called dynamic partial reconfiguration (DPR). A set of partial designs is created to fix the placement of a time-to-digital converter (TDC) and supporting infrastructure to enable the path delays through the target interconnect and switch matrices to be extracted by subtracting out common-mode delay components. Delay variations are analyzed in the different levels of routing resources available within FPGAs, i.e., local routing and across-chip routing. Data are collected from a set of Xilinx Zynq 7010 devices, and a statistical analysis of within-die variations in delay through a set of the randomly-generated and hand-crafted interconnects is presented.

Design and performance analysis of asynchronous network on chip for streaming data transmission on FPGA

The majority of the system on chip (SoC) uses the network on chip (NoC) as routing ports for data transfer from node-to-node with minimal power consumption and low latency and high throughput. This paper concentrates on the ability to model the asynchronous NoCs on the asynchronous circuits on field programmable gate arrays (FPGAs). A 3×3 NoC and its universal asynchronous receiver transmitter (UART) protocol is designed and its simulation of the Verilog hardware description language (VHDL) code is done and tested on the Artix-7 FPGA kit, the testing processes in done using the Chipscope tool. In order to meet target requirements in terms of power consumption and latency, the label switching (LS) technique is used as routing. The proposed LS-NoC with level-encoded dual-rail (LEDR) encoding technique provides throughput by registering the packet between the different routers and it helps to improve throughput and speed. The effectiveness of the data transfer is measured and analyzed through a synthesis summary in terms of lookup table’s (LUT’s), slice registers, flip flops’s (FF’s), latency, and packet delivery ratio (PDR) for the traffic pattern generator. The proposed NoC is designed for 8×8 and each port size is 21 bits including ID’s of source and destination routers. The results can be justified by following results: improvement of LUTs is about 12%, flip-flops are 7%, improvement of throughput is 23% and delay is reduced by 26%.

Gamificación como herramienta de marketing digital

This study addresses the need to improve customer retention and online interaction for "Flip Flop," a company with a customer base of 150 individuals dedicated to the production and marketing of footwear. The research focuses on implementing gamification as a strategic tool in digital marketing. The main objective is to determine the relationship between gamification and digital marketing to establish advertising strategies. The methodology followed a quantitative approach encompassing exploratory, descriptive, and correlational scopes. Data collection combined literature review with field research. Gamified strategies, including challenges and rewards, were implemented. The results revealed the significant relevance of gamification as a highly effective tool in digital marketing. To assess the impact of gamification on customer retention and online interaction, the level of acceptance of the strategy was evaluated, reaching a considerable 55.3% acceptance among surveyed customers. The quantitative approach, through questionnaires, facilitated data collection from potential customers, highlighting the strategic importance of gamification in generating audience interest and engagement. Gamification proved to be an effective strategy for enhancing the connection between the company and its customers, underscoring its valuable role in digital marketing. These findings emphasize the importance of innovation in this field and provide valuable insights for future research. In conclusion, gamification emerges as a crucial tool for enhancing the company-customer relationship in the context of digital marketing.

FPGA Acceleration of AES Algorithm for High-Performance Cryptographic Applications

This research paper presents the FPGA implementation of the AES-128 Algorithm as an accelerator tailored for high-performance cryptographic applications. Leveraging the capabilities of the Virtex-7 evaluation kit, the AES algorithm is meticulously coded using Xilinx Vivado software. The results of the implementation reveal a resource-efficient design, utilizing 588 Look-Up Tables (LUTs) and 353 Flip Flops. This implementation showcases the efficacy of FPGA technology, specifically the Virtex-7 device, in achieving a fine balance between algorithmic complexity and resource utilization for cryptographic acceleration. The abstract underscores the significance of this research in advancing the field of hardware-accelerated cryptographic applications, offering a scalable solution with promising resource efficiency on the FPGA platform.

Time to First Abrasion: A Comparative Evaluation of Flip Flop Strap Designs on Preserved Fetal Pig Skin and Implications for Dorsal Foot Health

Time to First Abrasion: A Comparative Evaluation of Flip Flop Strap Designs on Preserved Fetal Pig Skin and Implications for Dorsal Foot Health

Probability Driven Double-Edge Triggered Multibit Flip Flop and Clock Gating Integration

Abstract: The project delves into the using of Double Edge-Triggered Multi-Bit Flip-Flops (DETMBFFs) alongside Data Driven Clock Gating (DDCG) techniques to bolster power efficiency in digital circuit designs. DETMBFFs enable the data Capture on Both Up and Down Swings of a clock, optimizing throughput while conserving power. By grouping multiple flip-flops and employing a shared clock driver, DETMBFFs minimize redundant clock signals and reduce energy usage. The integration of DDCG selectively disables clock signals based on data activity, further enhancing power efficiency. A novel algorithm, grounded in the ratio of the data to clock toggling and probability-driven grouping of flip-flops within DETMBFFs, is developed to optimize power consumption. Through implementation using Xilinx software tool, the combined approach achieves remarkable power savings ranging from 17% to 23%. This creative approach not only enhances power efficiency but also maintains design integrity,making it a compelling solution for low-power design challenges in digital systems.

MS-LW-TI: Primitive-Based First-Order Threshold Implementation for 4 × 4 S-boxes

Threshold implementation (TI) is a lightweight countermeasure against side-channel attacks when glitches happen. As to masking schemes, an S-box is the key part to protection. In this paper, we propose a general first-order lightweight TI scheme for 4 × 4 S-boxes and name it as MiniSat-lightweight-threshold implementation (MS-LW-TI). First, we use MiniSat to optimally decompose an S-box into the least number of three different logic gate operations, AND, OR, and XOR. Among these operations, we define two primitives and the extension of two primitives for TI design. Furthermore, we prove that the primitives and their extensions strictly comply with the security properties. Finally, we implement MS-LW-TI on Xilinx Spartan-6 Field Programmable Gate Array (FPGA) to show that the S-boxes of PRESENT, GIFT, and PICCOLO consume only 17, 15, and 13 look-up-tables (LUTs), 16, 9, and 16 flip-flops (FFs), 6, 5, and 6 slices, respectively. Compared with the existing lightweight TI design, our TI for PRESENT S-box has a 22%, 38%, and 25% reduction of LUTs, FFs, and slices to the design by Shahmirzadi and Moradi at IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES) 2021, and our TI for GIFT S-box has a 6%, 25%, and 28% reduction of LUTs, FFs, and slices to the design by Jati et al., which is the smallest.

Parallel Gate Fidelity of Flip‐Flop Qubits in Small 1D‐ and 2D‐Arrays in a Noisy Environment

AbstractThe long coherence time of donor atom nuclear spin states and of its bounded electron in can be exploited to define a qubit. This work is focused on a type of donor‐ and quantum dot‐based qubit, the flip‐flop (FF) qubit, that leverages antiparallel electron‐nuclear spin states of a donor atom controlled by an electric field. It can provide long‐range inter‐qubit interactions in the order of some hundreds of nanometers, thus relaxing the common constraints and tolerances on inter‐qubit distances in donor‐based qubits. Simulation results of linear array (LA) and square array (SA) of four FF qubits are presented to study the effect of noise, idle qubits, and simultaneous gating (parallel gating) on gate fidelity. The impact of noise and qubit mutual coupling for both considered types of array are presented and the obtained fidelity results are compared.

Implementation of FPGA-based Accelerator for Convolutional Neural Networks

This research paper presents a novel FPGA-based accelerator tailored for Convolutional Neural Networks (CNNs), specifically implemented on the Virtex-7 evaluation kit. By harnessing the inherent parallel processing capabilities of FPGAs, the architecture of the accelerator is meticulously crafted using Verilog. The FPGA implementation demonstrates a resource-efficient design, making use of 588 Look-Up Tables (LUTs) and 353 Flip Flops. Notably, the efficient utilization of these resources signifies a careful balance between computational efficiency and the available FPGA resources. This research significantly contributes to the field of hardware acceleration for CNNs by offering an optimized solution for high-performance deep learning applications. The presented architecture serves as a promising foundation for future advancements in FPGA-based accelerators, providing valuable insights for researchers and engineers working in the domain of hardware optimization for Convolutional Neural Networks.

Agile Acceleration of Stateful Hash-based Signatures in Hardware

With the development of large-scale quantum computers, the current landscape of asymmetric cryptographic algorithms will change dramatically. Today’s standards like RSA, DSA, and ElGamal will no longer provide sufficient security against quantum attackers and need to be replaced with novel algorithms. In the face of these developments, NIST has already started a standardization process for new Key Encapsulation Mechanisms (KEMs) and Digital Signatures (DSs). Moreover, NIST has recommended the two stateful Hash-Based Signatures (HBSs) schemes XMSS and LMS for use in devices with a long expected lifetime and limited capabilities for maintenance. Both schemes are also standardized by the IETF. In this work, we present the first agile hardware implementation that supports both LMS and XMSS. Our design can instantiate either LMS, XMSS, or both schemes using a simple configuration setting. Leveraging the vast similarities of the two schemes, the hardware utilization of the agile design increases by 20% in LUTs and only 3% in Flip Flops (FFs) over a standalone XMSS implementation. Furthermore, our approach can easily be configured with an arbitrary number of hash cores and accelerators for the one-time signatures for different application scenarios. We evaluate our implementation on the Xilinx Artix-7 FPGA platform, which is the recommended target for PQC implementations by NIST. We explore potential tradeoffs in the design space and compare our results to previous work in this field.

Exploring Flip Flop memories and beyond: training Recurrent Neural Networks with key insights.

Training neural networks to perform different tasks is relevant across various disciplines. In particular, Recurrent Neural Networks (RNNs) are of great interest in Computational Neuroscience. Open-source frameworks dedicated to Machine Learning, such as Tensorflow and Keras have produced significant changes in the development of technologies that we currently use. This work contributes by comprehensively investigating and describing the application of RNNs for temporal processing through a study of a 3-bit Flip Flop memory implementation. We delve into the entire modeling process, encompassing equations, task parametrization, and software development. The obtained networks are meticulously analyzed to elucidate dynamics, aided by an array of visualization and analysis tools. Moreover, the provided code is versatile enough to facilitate the modeling of diverse tasks and systems. Furthermore, we present how memory states can be efficiently stored in the vertices of a cube in the dimensionally reduced space, supplementing previous results with a distinct approach.

Realization of an all-optical d and t flip flops with nano-structure using hybrid plasmonic waveguides

Realization of an all-optical d and t flip flops with nano-structure using hybrid plasmonic waveguides