Flip-chip Plastic Ball Grid Array Research Articles

P-WLCSP: 6-Side Protected WLCSP

The first silicon demonstration of 300mm P-WLCSP was introduced in 2021 at the 54th International Symposium on Microelectronics. This paper reports further developments and new test results for this low cost WLCSP approach to fully protected CSP. The paper briefly summarizes the evolution of protected CSP technology evolution as an introduction for a more extensive discussion of P-WLCSP. With the advent of bumped die new IC packages evolved: for low IO WLCSP (wafer level chip scale package) and for high IO FC (flip chip) CBGA (ceramic ball grid array) and PBGA (plastic ball grid array). For low IO, protected CSP is an emerging and rapidly growing market. In 2020 the market exceeded $2B and is ramping to a forecast $2.5B by 2025.1 Initially WLCSP, also known as FI (fan in), packages were built on the wafer with no active side protection evolving to 1 sided protection from a package built on the wafer2 which transition to redistribution PSB (passivation stress buffer)3, PSBs were used on FC wafers for high IO BGA packages. These provided acceptable performance initially, however as devices became more complex and reliability requirements increased, these processes no longer provided the required reliability. To attain higher IO capability and better reliability performance evolved to CSP (non WF) which allowed larger area for bump distribution and additional protection to the rest of the exposed die surfaces. Fully protected die CSP (without substrates or leadframes) was initially implemented with processes such as M-series utilizing a FO (fan out) process.5 To obtain higher reliability 6-sided die protection afforded by M-series type processes require die reconstitution, expensive tapes, molding operations required in a FO process that can be eliminated in a WLCSP protected FI process. American Semiconductor’s Semiconductor-on-Polymerâ?¢ (SoPâ?¢) 300mm FleX-TM P-WLCSP is an advanced packaging process optimized for protected fan-in. P-WLSCP ultra-thin fully protected chips will be shown from a wafer level process. Process development progress and test results will be presented.

Moisture Diffusion Inside the BEOL of an FC-PBGA Package

Moisture diffusion into the back-end-of-line (BEOL) can be critical for the reliability of electronic devices. With the objective of studying moisture diffusion into critical areas, such as the silicon–organic substrate interfaces of a flip chip plastic ball grid array (FC-PBGA), a multitude of impedance sensors sensitive to moisture are integrated inside the BEOL of a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$17\times17$ </tex-math></inline-formula> mm silicon die. The sensors are read by a dedicated custom circuit that allows accurate characterization of the moisture with in situ spatial measurements. This article presents the results obtained by the experimental acquisition system on the FC-PBGA module under a high-relative humidity (RH) level of up to 75%. This study shows the moisture behavior of the multiwalled carbon nanotube (MWCNT) sensors inside the BEOL during absorption and desorption. The behavior initially follows Fick’s law, with a constant increase in the RH. For long-term tests of more than 400 h, an asymptotic behavior is observed; when the concentration of a sensor reaches a value close to saturation, a two-dimensional finite-difference method (2D FDM) is used to estimate the saturation value. Thanks to the large number of sensors distributed on the BEOL, we first detect, during an absorption test, an increase in the RH. This increase is due, first of all, to a lateral moisture front with a constant velocity of about <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$90 ~\mu \text{m}$ </tex-math></inline-formula> /h moving through the underfill. Then, after 30 h of storage, a more complex diffusion through the organic substrate occurs, affecting the BEOL.

Advanced Protected Fan-In WLCSP

ABSTRACT With the advent of bumped die new IC packages evolved: for low IO WLCSP (wafer level chip scale package), for high IO FC (flip chip) CBGA (ceramic ball grid array) and PBGA (plastic ball grid array). For low IO, protected CSP is an emerging and rapidly growing market. In 2020 the market exceeded $2B and is ramping to a forecast $2.5B by 2025.1 Initially WLCSP, also known as FI (fan in), packages were built on the wafer with no active side protection evolving to single sided protection from a package built on the wafer2 which transition to redistribution PSB (passivation stress buffer)3, PSBs were used on FC wafers for high IO BGA packages. These provided acceptable performance initially, however as devices became more complex and reliability requirements increased, these processes no longer provided the required reliability. To attain higher IO capability and better reliability performance evolved to CSP4 (non-WL) which allowed larger area for bump distribution and additional protection to the rest of the exposed die surfaces. Fully protected die CSP (without substrates or leadframes) was initially implemented with processes such as M-series utilizing a FO (fan out) process.5 To obtain higher reliability 6-sided die protection afforded by M-series type processes require die reconstitution, expensive tapes, molding, and other operations generally required in a FO process which can feasibly be eliminated in a WLCSP protected FI process. American Semiconductor's Semiconductor-on-Polymer™ (SoP™) 300mm FleX-TM WLCSP is an advanced packaging process optimized for protected fan-in. FleX-TM produces the thinnest and lowest cost protected FI the industry today. Protected FI process innovations can improve performance in power devices, RF switches, die stacking and thin board applications. This article includes background on the evolution of CSP and the comparison of SOTA (state of the art) FI processes including FleX-TM.

Effect of Mechanical Properties of Joining Materials for Flip Chip on Thermo-mechanical Stress at Wiring Layer under Flip Chip Pad

Lead-free solders such as SnAg or SnAgCu is widely used for flip chip joining. As a result of higher melting temperature and higher elastic modulus of the lead-free solders compared to eutectic SnPb solder, defect of crack or damage in low-k dielectric layers under bond pad for flip chip joining in the semiconductor chip became a serious issue. The crack or damage is caused by mismatch of coefficient of thermal expansion (CTE) between chip and chip carrier substrate after chip join reflow. Various low melting temperature solders have been investigated and proposed as alternatives to SnAg or SnAgCu solders. Mechanical properties including creep properties are important factors as well as melting temperature for stress relief in micro joints and low-k layers.In this paper, the authors report measurement results of creep properties with fine-diameter-specimens (0.5 mm in diameter) of two low melting temperature solders (Sn-58Bi and In-3Ag) and conventional lead-free solder (Sn-3.0Ag-0.5Cu). The measurement matrix consists of four different strain rates and three different temperatures. The stress component n and the constant A in Norton's creep law were derived for each solder alloy. Then the stress analysis was performed with flip chip plastic ball grid array (FCPBGA) to evaluate stress at low-k dielectric layer under the bond pad using the obtained mechanical properties in this study.

散热强化型覆晶球栅数组组合体之锡球可靠度研究

本文探讨之散热强化型覆晶球栅数组组合体是基本型覆晶球栅数组封装体包封着封胶，接着在封胶上面黏附着一片铝质散热板，最后以锡球构装在印刷电路板上。凸块与锡球是锡铅合金属于黏塑材料，在文中的数值模拟中，是以亚兰德模型来定义并描述其弹性、塑性及潜变行为，其余组件是假设为弹性材料。本文使用有限元素分析软件ANSYS建立一精确之三维有限元素模型，于温度循环负载下，针对此组合体并搭配修正型Coffin-Manson疲劳寿命估算式进行锡球可靠度分析。本文报告了锡球应力、应变及疲劳寿命等机械行为。最后，进行參数化分析，探讨组合体组件的设计参数对锡球疲劳寿命的影响。结果表明：增加基板基材的热膨胀系数、杨氏系数与厚度可以提高锡球疲劳寿命。减少散热板膨胀系数、杨氏模数、厚度与宽度也会造成锡球寿命增加。增加封胶热膨胀系数或减少封胶杨氏模数会造成锡球疲劳寿命增加。黏着剂所占的体积小对锡球疲劳寿命的影响很小。在本文之研究范围内，减少热膨胀系数、减少杨氏模数及增大厚度有助于提升锡球疲劳寿命。 In this paper, the thermally enhanced FC-PBGA (Flip-Chip Plastic Ball Grid Array) assembly is a basic FC-PBGA package that is over-molded with molding compound, after which an aluminum heat spreader is adhered to the top of the molding compound and subsequently mounted on a PCB (Printed Circuit Board). Three-dimensional finite element analysis using the commercial ANSYS software is performed to study solder ball fatigue life for this thermally enhanced FC-PBGA as-sembly subjected to temperature cycling. In the simulation, all the solder bumps and the solder balls are modeled with nonlinear viscoplastic time and temperature dependent material properties based on Anand’s constitutive equation. Solder ball fatigue life is estimated by the widely accepted modified Coffin-Manson equation. The thermo-mechanical behavior of the assembly is pre- sented. Effects of alternative design parameters of the package components on solder ball fatigue life are analyzed. It is found that higher CTE of the substrate core, higher Young’s modulus of the substrate core, thicker substrate core, lower heat spreader CTE, lower heat spreader Young’s modulus, reduction of the thickness or width of the heat spreader, higher CTE of the molding compound and lower Young’s modulus of the molding compound result in better solder bump fatigue life. The effects of the parameters of the adhesive are found to have lesser impact on package reliability. However, lower CTE, lower Young’s modulus and greater thickness are found preferable.

Investigation of Thermal Characterization of a Thermally Enhanced FC-PBGA Assembly

In this paper, three-dimensional finite element analysis using the commercial ANSYS software is performed to study the thermal performance of a thermally enhanced FC-PBGA (flip-chip plastic ball grid array) assembly in both natural and forced convection environments. The thermally enhanced FC-PBGA assembly is a basic FC-PBGA assembly with a lid attached on top, after which an extruded-fin heatsink is attached on the top of the lid. The finite element model is complete enough to include key elements such as bumps, solder balls, substrate, printed circuit board, extruded-fin heatsink, lid, vias, TIM1 (thermal interface material 1), TIM2 (thermal interface material 2), lid-substrate adhesive and ground planes for both signal and power. Temperature fields are simulated and presented for several package configurations. Thermal resistance is calculated to characterize and compare the thermal performance by considering alternative design parameters of the polymer-based materials and the thermal enhancement components. The polymer-based materials include underfill, TIM1, TIM2, lid-substrate adhesive and substrate core material. The specific thermal enhancement components are the extruded-fin heatsink and the lid.

FEM Analysis on Warpage and Stress at the Micro Joint of Multiple Chip Stacking

Flip chip plastic ball grid array (FCPBGA) utilizing an interposer for multiple chip stacks, so called 2.5D or 3D package, is gaining prominence in order to achieve the next generation high performance computing. The multi-tier stacking of Si chip, Si interposer and organic substrate induces complicated warpage behavior and stress at the micro joints during the joining process. The authors studied warpage behavior and thermo-mechanical stress of multiple chip stacks on Si interposer package with different thickness of top chip, different thickness of Si interposer, different middle chip stacks and different metallurgy of micro joints after joining of stacked chips on the interposer using finite element method (FEM). Thicker stacked Si chips and thicker Si interposer showed higher von Mises stress at chip-to-interposer joint. Comparing SnAg joint and CuSn joint, CuSn joint always shows higher stress than SnAg joint because of its higher elastic modulus.

Numerical Study of Thermal Performance of FC-PBGA Assembly with Extruded-fin Heatsink

The trend in microelectronics is toward increasingly higher input/output, higher component density and higher electrical performance, which makes thermal enhancement of package performance an increasingly important issue. In both natural and forced convection environments, three-dimensional finite element simulation is used to study thermal performance of a flip-chip plastic ball grid array (FCPBGA) assembly with an extruded-fin heatsink on top of the assembly. The finite element model is complete enough to include key elements such as bumps, solder balls, substrate, printed circuit board, vias and ground planes for both signal and power. Temperature fields are simulated and presented for several FC-PBGA assembly configurations. Thermal resistance is calculated to characterize and compare the thermal performance by considering alternative design parameters of the extruded-fin heatsink and the lid.

Failure mechanism of FC-PBGA devices under external stress

Flip chip plastic ball grid array (FC-PBGA) is unique and has been widely used. During FC-PBGA's practical application, the analysis of its failure mechanisms under high temperature, electricity, water vapor and other comprehensive environmental stress conditions is very important for improving its application reliability. In this paper, with 0.13-μm m/6-level copper-based FPGA with FC-PBGA package, failure mode of the device is exposed under external stress, which is dominated with thermal-mechanical stress generated by high temperature thermal reflow process. And the failure mechanism corresponding to the failure mode is analyzed. Results show that the basic cause of the failure is the thermal-mechanical stress, which is induced by the combination of internal and external reflow temperature difference and high temperature reflow process when assembled. The thermal-mechanical stress makes the solder bumps on the flip chip melt again and bridges the adjacent solder bumps to lead to the device short failure. It also induces crack or delamination in the underfill, crack in solder bump or solder bump fallen off to lead to device open failure. The residual stress on Cu/low-k interconnect structures damages the structure integrity and affects the reliability of FC-PBGA packages.

Study of Warpage and Mechanical Stress of 2.5D Package Interposers during Chip and Interposer Mount Process

As data transmission rate increases, flip chip plastic ball grid array (FCPBGA) utilizing a interposer for multiple chips is gaining popularity because of high electrical performance, ease of chip design, ease of thermal management with thermal lid, etc. The authors assessed package design configuration and key design elements for two chips application assuming 1600 signal I/Os for logic and 800 signal I/Os for memory. Then, we studied warpage behavior of the interposer, and mechanical stress of solder interconnections and low-k dielectric layer under controlled collapse chip connection (C4) pad. We set three different mount process assumptions for chip to interposer and interposer to base organic substrate. The mount process assumptions are (1) two pass reflow of chip to interposer first, then interposer to base organic substrate, (2) reversed sequence of two pass reflow which is interposer to base organic substrate first, then chip to interposer, (3) one pass reflow of chip, interposer and base organic substrate all together. We also set three different interposer material assumptions of Si, glass and organic in this study. We analyzed warpage behavior and mechanical stress using finite element method (FEM) modeling technique with a set of combinations of coefficient of thermal expansion (CTE) and elastic modulus of the interposers. The study also includes an analysis for conventional multi-chip-module (MCM) FCPBGA as a reference. We show the analysis results of interposer warpage, first principal stress at low-k dielectric layer under C4 pad and von Mises stress at solder interconnections of chip joining and interposer joining.

散热强化型覆晶球栅数组封装组合体内的凸块之疲劳寿命研究 Investigation of Fatigue Life of Solder Bumps in a Thermally Enhanced FC-PBGA Assembly

使用有限元素分析软件ANSYS建立一精确之三维有限元素模型，于温度循环负载下，针对散热强化型覆晶球栅数组封装体中的凸块之热机械行为进行模拟分析，接着，对凸块之疲劳寿命进行预测。这个散热强化型覆晶球栅数组组合体是基本型覆晶球栅数组封装体包封着封胶，接着在封胶上面黏附着一片铝质散热板，最后以锡球构装在印刷电路板上。凸块与锡球的材料是锡铅合金,本文以亚兰德模型来定义并描述其弹性、塑性及潜变行为。凸块之疲劳寿命预测是将模拟得到的凸块Von-Mise应变范围代入修正型Coffin-Manson疲劳寿命预估式，来预估凸块之疲劳寿命。本文报告了凸块应力、应变及疲劳寿命等机械行为。最后，进行参数化分析,讨论不同高分子组件与散热组件的设计参数对凸块疲劳寿命的影响。 In this paper, three-dimensional finite element analysis using the commercial ANSYS software is performed to study solder bump fatigue life for a thermally enhanced FC-PBGA (Flip-Chip Plastic Ball Grid Array) assembly subjected to temperature cycling. The thermally enhanced FC-PBGA assembly is a basic FC-PBGA package that is overmolded with molding compound, after which an aluminum heat spreader is adhered to the top of the molding compound and subsequently mounted on a PCB (Printed Circuit Board). In the simulation, all the solder bumps and the solder balls are modeled with nonlinear viscoplastic time and temperature dependent material properties based on Anand’s constitutive equation. Solder bump fatigue life is estimated by the widely accepted modified Coffin-Manson equation. The thermo-mechanical behavior of the solder bumps is presented. Solder bump fatigue life is analyzed by considering various design parameters of the polymer-based materials and the thermal enhancement components.

Finite element based fatigue life estimation of the solder joints with effect of intermetallic compound growth

This paper develops an analysis procedure to study the effects of intermetallic compound (IMC) growth on the fatigue life of 63Sn–37Pb (lead-rich)/96.5Sn–3.5Ag (lead-free) solder balls for flip-chip plastic ball grid array packages under thermal cycling test conditions. In this analysis procedure, the thickness of the IMC increased with the number of thermal cycles, and was determined using the growth rate equation. A series of non-linear finite element analyses was conducted to simulate the stress/strain history at the critical locations of the solder balls with various IMC thicknesses in thermal cycling tests. The simulated stress/strain results were then employed in a fatigue life prediction model to determine the relationship between the predicted fatigue life of the solder ball and the IMC thickness. Based on the concept of continuous damage accumulation and incorporated with the linear damage rule, this study defines the damage of each thermal cycle as the reciprocal of the predicted fatigue life of the solder joints with the corresponding IMC thickness. The final fatigue failure of the solder ball was determined as the number of cycles corresponding to the cumulative damage equal to unity. Results show that the solder joint fatigue life decreased as the IMC thickness increased. Moreover, the predicted thermal fatigue life of lead-rich solders based on the effects of IMC growth is apparently smaller than that without considering the IMC growth in the reliability analysis. Results also show that the influence of the IMC thickness on the fatigue life prediction of the lead-free solder joint can be ignored.

Fracture mechanics study on the intermetallic compound cracks for the solder joints of electronic packages

The crack behavior of the intermetallic compounds (IMCs) for the solder joints of electronic packages under the thermal cycling test conditions was analyzed using the finite element method in this research. A flip-chip plastic ball grid array package was selected as the analysis target. The two-dimensional in-elastic finite element method was employed to calculate the fracture mechanics parameters at the crack tip; such as the modes I and II stress intensity factors. Two locations were considered herein to initiate the crack: the first one was on the interface between the IMC and the copper pad (interfacial cracks); and the other one was at the inner part of IMC (IMC cracks). Furthermore, the effects of crack length and thickness of IMC on the crack tip parameters were also studied in this investigation. In the numerical simulation, the properties of the solder joint and the underfill were assumed to be elastic–plastic–creep and viscoelastic, respectively. The sub-modeling technique was used in the finite element analysis to reduce the computational time and the crack tip parameters were obtained using the simulated results of the displacement field near the crack tips. The results show that for both interfacial cracks and the IMC cracks, the modes I and II SIFs decrease as the length of crack increases, and the decreasing trend becomes more stable when the cracks propagate longer except for the variation of the mode II SIF for IMC cracks. Furthermore, the thickness of the IMC has slight effect on the magnitudes of SIFs under the conditions of constant crack lengths.

Z-axis Interconnections for Next Generation Packaging

In this paper, the use of electrically conducting adhesives (ECA) to form z-axis interconnections for next generation packaging is discussed. In particular, current efforts related to Z-axis interconnections for device level fabrication, integration, and electrical performance are highlighted. A few optimized ECAs were used for hole fill applications to fabricate Z-axis interconnections in laminates. Conductive joints were formed during composite lamination using the ECA. Around 5,000 to 200,000 through holes in the joining cores, formed by laser or mechanical drilling, and having diameters ranging from 50 μm to 750 μm, were filled with an optimized conducting adhesive. The adhesive-filled joining cores/layers were laminated with circuitized subcomposites to produce a composite structure. As a case study, a variety of z-axis interconnect constructions for a flip-chip plastic ball grid array package, rigid-flex, rigid-rigid, package-interposer-package (PIP), RF structures, and PWBs were fabricated and evaluated at both the subcomposite and composite levels to understand structural and electrical integrity. Electrically, S-parameter measurements showed very low loss at multi-gigahertz frequencies. The losses were low enough to support typical SERDES up to 15 Gbps over 750 mm. The present process allows fabrication of z-interconnect conductive joints having diameters in the range of 55 to 500 μm. The processes and materials used to achieve smaller feature dimensions, satisfy stringent registration requirements, and achieve robust electrical interconnections are discussed.

Comparative Study of Phenolic-Based and Amine-Based Underfill Materials in Flip Chip Plastic Ball Grid Array Package

Phenolic and amine epoxy systems are widely used as hardeners in underfill materials for flip chip packaging. A comparison was made between these two systems in order to evaluate the reliability performance of a flip chip plastic ball grid array (FC-PBGA). The coefficient of thermal expansion, glass transition temperature (Tg), Young’s modulus (E), and fracture toughness were revealed by using a thermal mechanical analyzer, a dynamic mechanical analyzer, and a single-edge notch three-point bending test, while moisture absorption study was performed using an 85°C/85% relative humidity chamber. The adhesion strength with different conditions of temperature and humidity was performed using a die shear test. The series of standard reliability tests such as accelerated temperature cycle test, pressure cooker test, thermal humidity storage test, and high temperature storage test were executed upon the FC-PBGA, which was filled by phenolic and amine epoxy systems of underfill materials. It was found that the adhesion strength of phenolic-based underfills is better than that of amine-based underfills in almost all test conditions. Phenolic-based underfills also demonstrated better reliability compared with amine-based underfills.

Effect of Plasma Cleaning Process in the Wettability of Flip Chip PBGA Substrate of Integrated Circuit Packages

Effect of Plasma Cleaning Process in the Wettability of Flip Chip PBGA Substrate of Integrated Circuit Packages

A hybrid inverse method for evaluating FC-PBGA material response to thermal cycles

This study proposes a hybrid experimental-analytical inverse method that can be used to evaluate thermomechanical cyclic behavior of flip-chip plastic ball grid array modules and the constituent materials. Treating such a package as an adhesively bonded trilayer plate, the structural formulation follows and modifies an existing analytical model. A phase-shifted shadow moire method is employed to obtain the package thermal warpage variation in responding to a temperature cycle. By correlating the modeling predicted and the experimentally measured package warpage, the application of the method leads to the determination of those uncertain material parameters including temperature dependent modulus of elasticity and coefficient of thermal expansion of the die attachment and the substrate materials. These parameters are difficult to determine otherwise due to the complexity involving the effect of package processing condition and extremely thin thickness of the adhesive layer. As the values of all material parameters are ascertained, shear and peel stresses in the module adhesive layer can also be evaluated based on the analytical model.

Warpage Analysis of Flip-Chip PBGA Packages Subject to Thermal Loading

The aim of this paper was to measure and simulate the warpage of flip-chip PBGA packages subject to thermal loading (from room temperature to 260?C). In the experiments, a full-field shadow moirE? was used to measure real-time out-of-plane deformations (warpages) on the substrate and chip surfaces of the flip-chip packages under thermal heating and cooling conditions. A finite-element method (FEM) and Suhir's die-assembly theory, together with the measured material data (elastic moduli and coefficients of thermal expansion (CTEs) for organic substrates), were used to analyze the thermally induced deformations of the packages to gain insight into their mechanics. The strain gauge data used to determine the CTEs of the substrates also indicated that there was nearly no bending strain under thermal loading. The full-field warpages on the substrate surface of the packages from the shadow moirE? were documented under temperature loading. It was also found that there were different zero-warpage temperatures (which resulted in a variation of warpages at room temperature) for the four test packages during thermal loading, but they had similar warpage rates (the slope of warpage with respect to temperature). This might have been due to the creep of the underfill and the solder bumps in the packages at the solder reflow temperature. Regardless of the zero-warpage temperature, the warpage of the packages can be well simulated or predicted by FEM and Suhir's theory. The key material properties (elastic moduli and CTEs for the substrate and underfill) that affect the maximum warpage of the package were thoroughly studied. It was found that, among these material properties, a low elastic modulus for the underfill can significantly reduce the maximum warpage, while its CTE is much less sensitive to warpage. Moreover, the substrate CTE affects the warpage of a package only with noncompliant underfills, while a typical substrate elastic modulus (ranging from 10 to 30 GPa) is insensitive to warpage, unless its value is lower than a few gigapascals.

Effects of Phase Change of Pb-Free Flip-Chip Solders During Board-Level Interconnect Reflow

The impact of phase change (from solid to liquid) on the reliability of Pb-free flip-chip solders during board-level interconnect reflow is investigated. Most of the current candidates for Pb-free solder are tin-based with similar melting temperatures near 230 degC. Thus, Pb-free flip-chip solders melt again during the subsequent board-level interconnect reflow cycle. Solder volume expands more than 4% during the phase change from solid to liquid. The volumetric expansion of solder in a volume constrained by chip, substrate, and underfill creates serious reliability issues. The issues include underfill fracture and delamination from chip or substrate. Besides decreasing flip-chip interconnect reliability in fatigue, bridging through underfill cracks or delamination between neighboring flip-chip interconnects by the interjected solder leads to failures. In this paper, the volume expansion ratio of tin is experimentally measured, and a Pb-free flip-chip chip-scale package (FC-CSP) is used to observe delamination and solder bridging after solder reflow. It is demonstrated that the presence of molten solder and the interfacial failure of underfill can occur during solder reflow. Accordingly, Pb-free flip-chip packages have an additional reliability issue that has not been a concern for Pb solder packages. To quantify the effect of phase change, a flip-chip chip-scale plastic ball grid array package is modeled for nonlinear finite-element analysis. A unit-cell model is used to quantify the elongation strain of underfill and stresses at the interfaces between underfill and chip or underfill and substrate generated by volume expansion of solder. In addition, the strain energy release rate of interfacial crack between chip and underfill is also calculated

Effect of Size of Lid-Substrate Adhesive on Reliability of Solder Balls in Thermally Enhanced Flip Chip PBGA Packages

Six design cases of lid-substrate adhesive with various combinations of widths and heights were analyzed to investigate how the size of the adhesive affects the reliability of the solder balls of thermally enhanced flip chip plastic ball grid array (FC-PBGA) packages in thermal cycling tests. Analysis results were compared with data on the reliability of conventional FC-PBGA packages. Thermal-mechanical behavior was simulated by the finite element (FE) method and the eutectic solder was assumed to exhibit elastic-viscoplastic behavior. The temperature-dependent nonlinear stress/strain relationship of the adhesive was experimentally determined and used in the FE analysis. Darveaux's model was employed to obtain the predicted fatigue life of the solder ball. Simulation results reveal that the fatigue life of the solder balls in thermally enhanced FC-PBGA packages is much shorter than that in conventional FC-PBGA packages, and the life of solder balls increases with both the width and the height of the adhesive. However, the effect of the width of the adhesive on the reliability of the solder ball is stronger than that of the height. Moreover, increasing either the width or the height reduces the plastic strain in the adhesive at critical locations, indicating that the reliability of the adhesive can be improved by its size. The predicted results of the life of solder balls for some selected studied packages are also compared with experimental data from thermal cycling tests in the paper