Flip-chip Pad Research Articles

Effect of Mechanical Properties of Joining Materials for Flip Chip on Thermo-mechanical Stress at Wiring Layer under Flip Chip Pad

Lead-free solders such as SnAg or SnAgCu is widely used for flip chip joining. As a result of higher melting temperature and higher elastic modulus of the lead-free solders compared to eutectic SnPb solder, defect of crack or damage in low-k dielectric layers under bond pad for flip chip joining in the semiconductor chip became a serious issue. The crack or damage is caused by mismatch of coefficient of thermal expansion (CTE) between chip and chip carrier substrate after chip join reflow. Various low melting temperature solders have been investigated and proposed as alternatives to SnAg or SnAgCu solders. Mechanical properties including creep properties are important factors as well as melting temperature for stress relief in micro joints and low-k layers.In this paper, the authors report measurement results of creep properties with fine-diameter-specimens (0.5 mm in diameter) of two low melting temperature solders (Sn-58Bi and In-3Ag) and conventional lead-free solder (Sn-3.0Ag-0.5Cu). The measurement matrix consists of four different strain rates and three different temperatures. The stress component n and the constant A in Norton's creep law were derived for each solder alloy. Then the stress analysis was performed with flip chip plastic ball grid array (FCPBGA) to evaluate stress at low-k dielectric layer under the bond pad using the obtained mechanical properties in this study.

Development of Organic Multi Chip Package for High Performance Application

In recent years, it has become apparent that the conventional FC-BGA (Flip Chip Ball Grid Array) substrate manufacturing method (Electroless Cu plating, Desmear, Laser Drilling processing) is reaching its limits for finer wiring dimensions and narrower pitches of the flip chip pad. On the other hand, the demand for miniaturization and higher density continues to increase. Our solution is the Organic Multi Chip Package, a combined organic interposer and organic substrate. Unlike a conventional 2.5D interposer that is separately manufactured and then attached to a substrate PWB (Printed Wire Board), the interposer of our Organic Multi Chip Package is built directly onto an organic substrate. First normal build-up layers are laminated on both sides of the PWB core and metal traces formed by conventional semi-additive techniques. After the back side is coated with a typical SR layer for FC-BGA, the top surface and its laser-drilled vias are smoothed by CMP (Chemical Mechanical Polishing). A thin-film process is used to deposit the interposer's insulating resin layers. Then normal processes are applied to open small diameter vias and a metal seed layer is sputtered on. The wiring is patterned, and the metal traces are fully formed by plating. Finally, the Cu pads on the top layer are treated by OSP (Organic Solderability Preservative). In this paper we discuss results using a prototype 40 mm × 40 mm Organic Multi Chip Package. The prototype's organic substrate has a two-metal layer core with 100 μm diameter through-holes, two build-up layers on the chip side, and three plus a solder resist layer on the BGA side. The interposer has four wiring layers. Thus the structure of the prototype is 4+(2/2/3). For evaluation purposes, there are four patterns of lines and spaces on the interposer: 2 μm/2 μm, 3 μm/3 μm, 4 μm/4 μm, and 5 μm/5 μm. The metal trace thicknesses are 2.5 μm, via diameters are 10 μm, pad pitches are 40 μm, and the Cu pad diameters are 25 μm. These dimensions allow the Organic Multi Chip Package to easily make the pitch conversions of the IC to the PCB. With a 4+(2/2/3) structure, the Organic Multi Chip Package is asymmetric, raising concerns about package warping. However, the warping can be reduced by the optimization of structure and materials. In this way, we were able to connect a high pin-count logic chip to standard Wide I/O memory chips. We think that there are at least two obvious advantages of the Organic Multi Chip Package. The first is a total height reduction compared to a structure with a separate silicon interposer attached to a PWB substrate. The Organic Multi Chip Package, with its built-on interposer, eliminates the need for solder joints between the interposer and substrate. In addition, the fine resin layers make our interposer much thinner than a silicon interposer. The second advantage is simpler assembly. Our structure does not require the separate step of assembling an interposer to the substrate. Assembly costs should be lower and yields higher. In this paper we demonstrate the successful attainment of fine lines and spaces on the Organic Multi Chip Package. We also show and discuss reliability test results.

Electromigration Reliability of Glass Ceramic Multilayer Substrate with Various Surface Finishes

The process speed of high-end servers and supercomputers are steadily increasing. As a result, the backbone of the high speed processing, such as high-end LSI (flip-chip type), and associated substrate circuits is also becoming more dense and miniaturized, while supporting higher current densities. However, recent studies indicate that the higher current density triggers an electromigration (EM) at the solder bumps connecting the under bump metallurgy (UBM) of the flip-chip pad (e.g. Ni) and substrate pads (e.g. Ni/Au). This electromigration leads to voids within the solder joints, which may result in an open circuit. As of result, the life-cycle of the packaged devices is shortened. Thus solution to the EM issue is critical. To respond to such concerns, we have studied the mechanism of the void development, by closely examining differences in diffusion rate among the connective metals - within the pads and the solders. We have mitigated the EM occurrence by reducing the differences in diffusion rate by utilizing high purity Cu for the substrate metallization pads, Cu exhibits a diffusion rate similar to Sn used in solder bumps. Also, solder wettability was improved by utilizing a solder on pad (SOP) construction. As of result we were able to successfully demonstrate an improved life-cycle of the flip-chip solder joints, while accommodating a higher current density. Furthermore, a glass ceramic substrate was used for our study. Since this particular glass ceramic substrate has a coefficient of thermal expansion of 11.8ppm/K, there is an improvement in 1st and 2nd level reliabilities associated with thermal stress from device heat generation. At the same time, it possesses a dielectric constant of 5.8, which is conductive with superior electrical performance (high speed and high frequency). Thus, this glass ceramic substrate is capable of supporting increases in current density, while sustaining high reliability.

Integrated Hardware and Software for Improved Flatness Measurement With ATC4.1 Flip-Chip Assembly Case Study

Over the past four decades, microelectronic packaging technology has evolved from peripheral, through-hole, and bulk configurations to area-array, surface-mount, and small-profile ones. Among these approaches, flip-chip attachment has become the most favorable choice for its large input/output capabilities and short signal path distributions. Given the prediction that the chip size and power of a single chip package will increase dramatically, substrate warpage of flip-chip packages during assembly and usage has become a major concern. Warpage could cause misalignment between the chip and the substrate, prevent the solder balls from making contact with the substrate flip-chip pads during the reflow soldering process, and induce crack nucleation at the board underfill interface during long-term usage. In this paper, the authors developed an integrated large-area shadow moire system for measuring small and large board and chip package warpage. The hardware is designed to carry out warpage measurement with a resolution on the order of micrometers. Combined with software, the integrated system is fully automated and highly accurate. For the case study, the system is used to characterize the substrate warpage of flip-chip on organic board assemblies. Warpage of substrates at the initial bare-board stage, post-reflow, and post-underfill is measured at room temperatures. It is found that by properly selecting initially warped substrates, post-reflow and post-underfill warpage can be reduced. In addition, warpage measurements at elevated temperatures during thermal cycling and power cycling show that power cycling poses a smaller impact on substrate warpage.

Features of new laser micro-via organic substrate for semiconductor package

An introduced new substrate technology for semiconductor packaging by flip chip bonding has featured with following design deliverables. The conductor line width is 25 μm and the space between the lines is 25 μm minimum at an escape point between flip chip pads. The thickness of dielectric layer is adjusted to obtain characteristic impedance with 50 Ω. A film resin for dielectric is applied to a base core sequentially with conductor plane alternately and laser-drilled micro-via hole is formed in the resin to connect conductor planes. UV-laser drill is employed to provide micro-via hole with 48 μm as drilled. The conductor layers are formed with copper pulse-pattern plating after electroless seed layer plating. The substrate passed JEDEC level-3 stress test and 10 GHz clock frequency possibility was demonstrated.

Semiconductor Chip Attachment with Small Bump Flip Chips

It has been reported that the ratio of the diameter to the height of a reflow soldered flip-chip pad should be less than 2:l [1], [2]. This geometry permits a ductile material to accept the strain caused by differences in thermal expansion coefficients of silicon and alumina. However, to deposit sufficient material on a semiconductor chip to achieve this geometry has usually meant chip pad redesign and the resulting costly mask changes. This paper describes methods of depositing SUfficient material on a thick film substrate to permit use of chips with reduced bump volume. Details in the paper describe the volume calculations and artwork design for deposition of solder creme by screen printing. Selection and deposition of a dielectric glaze material to limit the area Of solder wetting on the substrate pads in also described. The test vehicle used in the study is a simple 2-bit counter utilizing 14MECL gates. It was fabricated in multilayer format for comparison of operating parameters between eutectic back bonded and solder reflow face bonded chips.